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sgus050a ? january 2004 ? revised march 2004 1 post office box 1443 ? houston, texas 77251?1443 highest-performance fixed-point digital signal processors (dsps) ? 2-, 1.67-, 1.39-ns instruction cycle time ? 600-mhz clock rate ? eight 32-bit instructions/cycle ? twenty-eight operations/cycle ? 4800 mips ? fully software-compatible with c62x ? ? c6414/15/16 devices pin-compatible velociti.2 ? extensions to velociti ? advanced very-long-instruction-word (vliw) tms320c64x ? dsp core ? eight highly independent functional units with velociti.2 ? extensions: ? six alus (32-/40-bit), each supports single 32-bit, dual 16-bit, or quad 8-bit arithmetic per clock cycle ? two multipliers support four 16 x 16-bit multiplies (32-bit results) per clock cycle or eight 8 x 8-bit multiplies (16-bit results) per clock cycle ? non-aligned load-store architecture ? 64 32-bit general-purpose registers ? instruction packing reduces code size ? all instructions conditional instruction set features ? byte-addressable (8-/16-/32-/64-bit data) ? 8-bit overflow protection ? bit-field extract, set, clear ? normalization, saturation, bit-counting ? velociti.2 ? increased orthogonality viterbi decoder coprocessor (vcp) [c6416] ? supports over 500 7.95-kbps amr ? programmable code parameters turbo decoder coprocessor (tcp) [c6416] ? supports up to six 2-mbps 3gpp (6 iterations) ? programmable turbo code and decoding parameters l1/l2 memory architecture ? 128k-bit (16k-byte) l1p program cache (direct mapped) ? 128k-bit (16k-byte) l1d data cache (2-way set-associative) ? 8m-bit (1024k-byte) l2 unified mapped ram/cache (flexible allocation) two external memory interfaces (emifs) ? one 64-bit (emifa), one 16-bit (emifb) ? glueless interface to asynchronous memories (sram and eprom) and synchronous memories (sdram, sbsram, zbt sram, and fifo) ? 1280m-byte total addressable external memory space enhanced direct-memory-access (edma) controller (64 independent channels) host-port interface (hpi) ? user-configurable bus width (32-/16-bit) 32-bit/33-mhz, 3.3-v pci master/slave interface conforms to pci specification 2.2 [c6415/c6416 ] ? three pci bus address registers: prefetchable memory non-prefetchable memory i/o ? four-wire serial eeprom interface ? pci interrupt request under dsp program control ? dsp interrupt via pci i/o cycle three multichannel buffered serial ports ? direct interface to t1/e1, mvip, scsa framers ? up to 256 channels each ? st-bus-switching-, ac97-compatible ? serial peripheral interface (spi) compatible (motorola ? ) three 32-bit general-purpose timers universal test and operations phy interface for atm (utopia) [c6415/c6416] ? utopia level 2 slave atm controller ? 8-bit transmit and receive operations up to 50 mhz per direction ? user-defined cell format up to 64 bytes sixteen general-purpose i/o (gpio) pins flexible pll clock generator ieee-1149.1 (jtag ? ) boundary-scan-compatible 570-pin grid array (pga) package (gad suffix) 0.13- m/6-level c u metal process (cmos) 3.3-v i/os, 1.4-v internal please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications o f texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 2004, texas instruments incorporated c62x, velociti.2, velociti, and tms320c64x are trademarks of texas instruments. motorola is a trademark of motorola, inc. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture.
sgus050a ? january 2004 ? revised march 2004 2 post office box 1443 ? houston, texas 77251?1443 table of contents bootmode 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 76 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 76 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 77 . recommended clock and control signal transition behavior 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 78 . . . . . . . . . . . . . . . input and output clocks 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 84 . . . . . . . . . . . . . . . . . . . . . programmable synchronous interface timing 88 . . . . . . . . synchronous dram timing 93 . . . . . . . . . . . . . . . . . . . . . . . . hold /holda timing 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . busreq timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface (hpi) timing 108 . . . . . . . . . . . . . . . . . . . peripheral component interconnect (pci) timing [c6415 and c6416 only] 113 . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port (mcbsp) timing 116 . . . . utopia slave timing [c6415 and c6416 only] 124 . . . . . . timer timing 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (gpio) port timing 128 . . . . jtag test-port timing 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gad pga package (bottom view) 3 . . . . . . . . . . . . . . . . . . . . . description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device compatibility 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and cpu (dsp core) diagram 7 . . . . . . . . . . . cpu (dsp core) description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 13 . . . . . . . . . . . . . . . . . . . . . . . edma channel synchronization events 26 . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 28 . . . . . . . . . . . . . . . . signal groups description 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplexed pins 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock pll 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (gpio) 70 . . . . . . . . . . . . . . . . . . power-down mode logic 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 jtag compatibility statement 74 . . . . . . . . . . . . . emif device speed 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sgus050a ? january 2004 ? revised march 2004 3 post office box 1443 ? houston, texas 77251?1443 revision history this data sheet revision history highlights the technical changes made to the smj320c6414, smj320c6415, and smj320c6416 device-specific data sheet. scope: applicable updates to the c64x device family, specifically relating to the c6414, c6415, and c6416 devices, have been incorporated. page(s) no. additions/changes/deletions all original release 3, 81, 82, 83 removed pin a24, changed cycle-to-cycle jitter to period jitter. gad ceramic pga package (bottom view) gad ceramic 570-pin grid array (pga) package ( bottom view ) 10 5 3 1 246 7 8 919 14 12 11 13 17 16 15 18 24 21 20 22 23 c a b u k f e d g j h n l m r t p ad y w v aa ac ab
sgus050a ? january 2004 ? revised march 2004 4 post office box 1443 ? houston, texas 77251?1443 description the tms320c64x ? dsps (including the smj320c6414, smj320c6415, and smj320c6416 devices) are the highest-performance fixed-point dsp generation in the tms320c6000 ? dsp platform. the tms320c64x ? (c64x ? ? ) device is based on the second-generation high-performance, advanced velociti ? very-long-instruction-word (vliw) architecture (velociti.2 ? ) developed by texas instruments (ti), making these dsps an excellent choice for multichannel and multifunctional applications. the c64x ? is a code-compatible member of the c6000 ? dsp platform. with performance of up to 5760 million instructions per second (mips) at a clock rate of 720 mhz, the c64x devices offer cost-effective solutions to high-performance dsp programming challenges. the c64x dsps possess the operational flexibility of high-speed controllers and the numerical capability of array processors. the c64x ? dsp core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (alus)? with velociti.2 ? extensions. the velociti.2 ? extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the velociti ? architecture. the c64x can produce four 32-bit multiply-accumulates (macs) per cycle for a total of 2400 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 4800 mmacs. the c64x dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other c6000 ? dsp platform devices. the c6416 device has two high-performance embedded coprocessors [viterbi decoder coprocessor (vcp) and turbo decoder coprocessor (tcp)] that significantly speed up channel-decoding operations on-chip. the vcp operating at cpu clock divided-by-4 can decode over 500 7.95-kbps adaptive multi-rate (amr) [k = 9, r = 1/3] voice channels. the vcp supports constraint lengths k = 5, 6, 7, 8, and 9, rates r = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. the tcp operating at cpu clock divided-by-2 can decode up to thirty-six 384-kbps or six 2-mbps turbo encoded channels (assuming 6 iterations). the tcp implements the max*log-map algorithm and is designed to support all polynomials and rates required by third-generation partnership projects (3gpp and 3gpp2), with fully programmable frame length and turbo interleaver. decoding parameters such as the number of iterations and stopping criteria are also programmable. communications between the vcp/tcp and the cpu are carried out through the edma controller. the c64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. the level 1 program cache (l1p) is a 128k-bit direct mapped cache and the level 1 data cache (l1d) is a 128k-bit 2-way set-associative cache. the level 2 memory/cache (l2) consists of an 8m-bit memory space that is shared between program and data space. l2 memory can be configured as mapped memory or combinations of cache (up to 256k bytes) and mapped memory. the peripheral set includes three multichannel buffered serial ports (mcbsps); an 8-bit universal test and operations phy interface for asynchronous t ransfer mode (atm) slave [ut opia slave] port (c6415/c6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (hpi16/hpi32); a peripheral component interconnect (pci) [c6415/c6416 only]; a general-purpose input/output port (gpio) with 16 gpio pins; and two glueless external memory interfaces (64-bit emifa and 16-bit emifb ? ), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. the c64x has a complete set of development tools which includes: an advanced c compiler with c64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. tms320c6000, c64x, and c6000 are trademarks of texas instruments. windows is a registered trademark of the microsoft corporation. all trademarks are the property of their respective owners. ? throughout the remainder of this document, the smj320c6414, smj320c6415, and smj320c6416 shall be referred to as smj320c64x or c64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as c6414, c6415, or c6416. ? these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name.
sgus050a ? january 2004 ? revised march 2004 5 post office box 1443 ? houston, texas 77251?1443 device characteristics table 1 provides an overview of the c6414, c6415, and c6416 dsps. the table shows significant features of the c64x devices, including the capacity of on-chip ram, the peripherals, the cpu frequency, and the package type with pin count. table 1. characteristics of the c6414, c6415, and c6416 processors hardware features c6414, c6415, and c6416 emifa (64-bit bus width) (default clock source = aeclkin) 1 peripherals emifb (16-bit bus width) (default clock source = beclkin) 1 peripherals not all peripherals pins edma (64 independent channels) 1 not all peripherals pins are available at the same hpi (32- or 16-bit user selectable) 1 (hpi16 or hpi32) are available at the same time. (for more details, see the device pci (32-bit) [deviceid register value 0xa106] 1 [c6415/c6416 only] time. (for more details, see the device configuration section.) peripheral performance is mcbsps (default internal clock source = cpu/4 clock frequency) 3 peripheral performance is dependent on chip-level utopia (8-bit mode) 1 [c6415/c6416 only] dependent on chip-level configuration. 32-bit timers (default internal clock source = cpu/8 clock frequency) 3 general-purpose input/output 0 (gp0) 16 decoder coprocessors vcp 1 (c6416 only) decoder coprocessors tcp 1 (c6416 only) size (bytes) 1056k on-chip memory organization 16k-byte (16kb) l1 program (l1p) cache 16kb l1 data (l1d) cache 1024kb unified mapped ram/cache (l2) cpu id + cpu rev id control status register (csr.[31:16]) 0x0c01 device_id silicon revision identification register (device_rev [19:16]) address: 0x01b0 0200 device_rev[19:16] silicon revision 1111 1.03 or earlier 0001 1.03 0010 or 0000 1.1 frequency mhz 600 cycle time ns 1.67 ns (c6414, c6415, c6416) and (c6414a, c6415a, c6416a) [600-mhz cpu, 133-mhz emifa] ? voltage core (v) 1.4 v voltage i/o (v) 3.3 v pll options clkin frequency multiplier bypass (x1), x6, x12 pga package 33 x 33 mm 570-pin pga (gad) process technology m 0.13 m product status product preview (pp) advance information (ai) production data (pd) pd ? on these c64x ? devices, the rated emif speed affects only the sdram interface on emifa. for more detailed information, see the emif device speed section of this data sheet.
sgus050a ? january 2004 ? revised march 2004 6 post office box 1443 ? houston, texas 77251?1443 device compatibility the c64x ? generation of devices has a diverse and powerful set of peripherals. the common peripheral set and pin-compatibility that the c6414, c6415, and c6416 devices offer lead to easier system designs and faster time to market. table 2 identifies the peripherals and coprocessors that are available on the c6414, c6415, and c6416 devices. the c6414, c6415, and c6416 devices are pin-for-pin compatible, provided the following conditions are met: all devices are using the same peripherals. the c6414 is pin-for-pin compatible with the c6415/c6416 when the pci and utopia peripherals on the c6415/c6416 are disabled. the c6415 is pin-for-pin compatible with the c6416 when they are in the same peripheral selection mode. [for more information on peripheral selection, see the device configurations section of this data sheet.] the bea[9:7] pins are properly pulled up/down. [for more details on the device-specific bea[9:7] pin configurations, see the terminal functions table of this data sheet.] table 2. peripherals and coprocessors available on the c6414, c6415, and c6416 devices ?? peripherals/coprocessors c6414 c6415 c6416 emifa (64-bit bus width) emifb (16-bit bus width) edma (64 independent channels) hpi (32- or 16-bit user selectable) pci (32-bit) [specification v2.2] ? mcbsps (mcbsp0, mcbsp1, mcbsp2) utopia (8-bit mode) [specification v1.0] ? timers (32-bit) [timer0, timer1, timer2] gpios (gp[15:0]) vcp/tcp coprocessors ? ? ? ? denotes peripheral/coprocessor is not available on this device. ? not all peripherals pins are available at the same time. (for more details, see the device configuration section.) for more detailed information on the device compatibility and similarities/differences among the c6414, c6415, and c6416 devices, see the how to begin development today with the tms320c6414, tms320c6415, and tms320c6416 dsps application report (literature number spra718).
sgus050a ? january 2004 ? revised march 2004 7 post office box 1443 ? houston, texas 77251?1443 functional block and cpu (dsp core) diagram emif b 16 64 test c64x dsp core data path b b register file b31?b16 b15?b0 instruction fetch instruction dispatch advanced instruction packet instruction decode data path a a register file a31?a16 a15?a0 power-down logic .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 sdram fifo sbsram sram l1p cache direct-mapped 16k bytes total control registers control logic l1d cache 2-way set-associative 16k bytes total advanced in-circuit emulation interrupt control mcbsps: framing chips: h.100, mvip, scsa, t1, e1 ac97 devices, spi devices, codecs c64x digital signal processor enhanced dma controller (64-channel) 32 l2 memory 1024k bytes pll (x1, x6, x12) timer 2 emif a mcbsp1 ? mcbsp0 hpi ? zbt sram timer 1 timer 0 mcbsp2 boot configuration interrupt selector 16 rom/flash i/o devices pci ? or gpio[8:0] utopia ? or gpio[15:9] ? utopia: up to 400 mbps master atmc ? vcp and tcp decoder coprocessors are applicable to the c6416 device only. ? for the c6415 and c6416 devices, the utopia peripheral is muxed with mcbsp1, and the pci peripheral is muxed with the hpi peripheral and the gpio[15:9] port. for more details on the multiplexed pins of these peripherals, see the device configurations section of this data sheet. vcp ? tcp ?
sgus050a ? january 2004 ? revised march 2004 8 post office box 1443 ? houston, texas 77251?1443 cpu (dsp core) description the cpu fetches v elociti ? advanced very-long instruction words (vliws) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. the velociti ? vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the c64x cpus from other vliw architectures. the c64x ? velociti.2 ? extensions add enhancements to the tms320c62x ? dsp velociti ? architecture. these enhancements include: register file enhancements data path extensions quad 8-bit and dual 16-bit extensions with data flow enhancements additional functional unit hardware increased orthogonality of the instruction set additional instructions that reduce code size and increase register flexibility the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. in addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the c62x ? velociti ? vliw architecture, the c64x ? register files also support packed 8-bit data and 64-bit fixed-point data types. the two sets of functional units, along with two register files, compose sides a and b of the cpu [see the functional block and cpu (dsp core) diagram, and figure 1]. the four functional units on each side of the cpu can freely share the 32 registers belonging to that side. additionally, each side features a ?data cross path??a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. the c64x cpu pipelines data-cross-path accesses over multiple clock cycles. this allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. all functional units in the c64x cpu can access operands via the data cross path. register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle. on the c64x cpu, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. in addition to the c62x ? dsp fixed-point instructions, the c64x ? dsp includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. these velociti.2 ? extensions allow the c64x cpu to operate directly on packed data to streamline data flow and increase instruction set efficiency. another key feature of the c64x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the c64x .d units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. and with the new data path extensions, the c64x .d unit can load and store doublewords (64 bits) with a single instruction. furthermore, the non-aligned load and store instructions allow the .d units to access words and doublewords on any byte boundary. the c64x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 64 registers. some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically ?true?). tms320c62x is a trademark of texas instruments.
sgus050a ? january 2004 ? revised march 2004 9 post office box 1443 ? houston, texas 77251?1443 cpu (dsp core) description (continued) the two .m functional units perform all multiplication operations. each of the c64x .m units can perform two 16 16-bit multiplies or four 8 8-bit multiplies per clock cycle. the .m unit can also perform 16 32-bit multiply operations, dual 16 16-bit multiplies with add/subtract operations, and quad 8 8-bit multiplies with add operations. in addition to standard multiplies, the c64x .m units include bit-count, rotate, galois field multiplies, and bidirectional variable shift hardware. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the arithmetic and logical functions on the c64x cpu include single 32-bit, dual 16-bit, and quad 8-bit operations. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are ?linked? together by ?1? bits in the least significant bit (lsb) position of the instructions. the instructions that are ?chained? together for simultaneous execution (up to eight in total) compose an execute packet. a ?0? in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. a c64x ? dsp device enhancement now allows execute packets to cross fetch-packet boundaries. in the tms320c62x ? /tms320c67x ? dsp devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. in the c64x ? dsp device, the execute boundary restrictions have been removed, thereby, eliminating all of the nops added to pad the fetch packet, and thus, decreasing the overall code size. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. all load and store instructions are byte-, half-word-, word-, or doubleword-addressable. for more details on the c64x cpu functional units enhancements, see the following documents: the tms320c6000 cpu and instruction set reference guide (literature number spru189) tms320c64x technical overview (literature number spru395) how to begin development today with the tms320c6414, tms320c6415, and tms320c6416 dsps application report (literature number spra718) tms320c67x is a trademark of texas instruments.
sgus050a ? january 2004 ? revised march 2004 10 post office box 1443 ? houston, texas 77251?1443 cpu (dsp core) description (continued) .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 src1 long dst 8 8 src2 da1 (address) st1b (store data) st2a (store data) register file a (a0?a31) 8 8 8 8 dst data path a da2 (address) register file b (b0? b31) ld2a (load data) data path b control register file st2b (store data) ld1b (load data) 8 8 2x 1x st1a (store data) see note a see note a ld1a (load data) ld2b (load data) see note a see note a 32 msbs 32 lsbs 32 msbs 32 lsbs 32 msbs 32 lsbs 32 msbs 32 lsbs src2 src1 dst long dst long src long src long dst dst src1 src2 src1 src2 src2 src1 dst src2 src1 dst src2 long dst src2 src1 dst long dst long dst long src long src long dst dst dst src2 src1 dst note a: for the .m functional units, the long dst is 32 msbs and the dst is 32 lsbs. figure 1. smj320c64x ? cpu (dsp core) data paths
sgus050a ? january 2004 ? revised march 2004 11 post office box 1443 ? houston, texas 77251?1443 memory map summary table 3 shows the memory map address ranges of the smj320c64x device. internal memory is always located at address 0 and can be used as both program and data memory. the external memory address ranges in the c64x device begin at the hex address locations 0x6000 0000 for emifb and 0x8000 0000 for emifa.
sgus050a ? january 2004 ? revised march 2004 12 post office box 1443 ? houston, texas 77251?1443 memory map summary (continued) table 3. smj320c64x memory map summary memory block description block size (bytes) hex address range internal ram (l2) 1m 0000 0000 ? 000f ffff reserved 23m 0010 0000 ? 017f ffff external memory interface a (emifa) registers 256k 0180 0000 ? 0183 ffff l2 registers 256k 0184 0000 ? 0187 ffff hpi registers 256k 0188 0000 ? 018b ffff mcbsp 0 registers 256k 018c 0000 ? 018f ffff mcbsp 1 registers 256k 0190 0000 ? 0193 ffff timer 0 registers 256k 0194 0000 ? 0197 ffff timer 1 registers 256k 0198 0000 ? 019b ffff interrupt selector registers 256k 019c 0000 ? 019f ffff edma ram and edma registers 256k 01a0 0000 ? 01a3 ffff mcbsp 2 registers 256k 01a4 0000 ? 01a7 ffff emifb registers 256k 01a8 0000 ? 01ab ffff timer 2 registers 256k 01ac 0000 ? 01af ffff gpio registers 256k 01b0 0000 ? 01b3 ffff utopia registers (c6415 and c6416 only) ? 256k 01b4 0000 ? 01b7 ffff tcp/vcp registers (c6416 only) ? 256k 01b8 0000 ? 01bb ffff reserved 256k 01bc 0000 ? 01bf ffff pci registers (c6415 and c6416 only) ? 256k 01c0 0000 ? 01c3 ffff reserved 4m ? 256k 01c4 0000 ? 01ff ffff qdma registers 52 0200 0000 ? 0200 0033 reserved 736m ? 52 0200 0034 ? 2fff ffff mcbsp 0 data 64m 3000 0000 ? 33ff ffff mcbsp 1 data 64m 3400 0000 ? 37ff ffff mcbsp 2 data 64m 3800 0000 ? 3bff ffff utopia queues (c6415 and c6416 only) ? 64m 3c00 0000 ? 3fff ffff reserved 256m 4000 0000 ? 4fff ffff tcp/vcp (c6416 only) ? 256m 5000 0000 ? 5fff ffff emifb ce0 64m 6000 0000 ? 63ff ffff emifb ce1 64m 6400 0000 ? 67ff ffff emifb ce2 64m 6800 0000 ? 6bff ffff emifb ce3 64m 6c00 0000 ? 6fff ffff reserved 256m 7000 0000 ? 7fff ffff emifa ce0 256m 8000 0000 ? 8fff ffff emifa ce1 256m 9000 0000 ? 9fff ffff emifa ce2 256m a000 0000 ? afff ffff emifa ce3 256m b000 0000 ? bfff ffff reserved 1g c000 0000 ? ffff ffff ? for the c6414 device, these memory address locations are reserved. the c6414 device does not support the utopia and pci peripherals. ? only the c6416 device supports the vcp/tcp coprocessors. for the c6414 and c6415 devices, these memory address locations are reserve d.
sgus050a ? january 2004 ? revised march 2004 13 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions table 4 through table 23 identify the peripheral registers for the c6414, c6415, and c6416 devices by their register names, acronyms, and hex address or hex address range. for more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the tms320c6000 dsp peripherals overview reference guide (literature number spru190). table 4. emifa registers hex address range acronym register name 0180 0000 gblctl emifa global control 0180 0004 cectl1 emifa ce1 space control 0180 0008 cectl0 emifa ce0 space control 0180 000c ? reserved 0180 0010 cectl2 emifa ce2 space control 0180 0014 cectl3 emifa ce3 space control 0180 0018 sdctl emifa sdram control 0180 001c sdtim emifa sdram refresh control 0180 0020 sdext emifa sdram extension 0180 0024 ? 0180 003c ? reserved 0180 0040 pdtctl peripheral device transfer (pdt) control 0180 0044 cesec1 emifa ce1 space secondary control 0180 0048 cesec0 emifa ce0 space secondary control 0180 004c ? reserved 0180 0050 cesec2 emifa ce2 space secondary control 0180 0054 cesec3 emifa ce3 space secondary control 0180 0058 ? 0183 ffff ? reserved table 5. emifb registers hex address range acronym register name 01a8 0000 gblctl emifb global control 01a8 0004 cectl1 emifb ce1 space control 01a8 0008 cectl0 emifb ce0 space control 01a8 000c ? reserved 01a8 0010 cectl2 emifb ce2 space control 01a8 0014 cectl3 emifb ce3 space control 01a8 0018 sdctl emifb sdram control 01a8 001c sdtim emifb sdram refresh control 01a8 0020 sdext emifb sdram extension 01a8 0024 ? 01a8 003c ? reserved 01a8 0040 pdtctl peripheral device transfer (pdt) control 01a8 0044 cesec1 emifb ce1 space secondary control 01a8 0048 cesec0 emifb ce0 space secondary control 01a8 004c ? reserved 01a8 0050 cesec2 emifb ce2 space secondary control 01a8 0054 cesec3 emifb ce3 space secondary control 01a8 0058 ? 01ab ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 14 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 6. l2 cache registers hex address range acronym register name comments 0184 0000 ccfg cache configuration register 0184 0004 ? 0184 0ffc ? reserved 0184 1000 edmaweight l2 edma access control register 0184 1004 ? 0184 1ffc ? reserved 0184 2000 l2alloc0 l2 allocation register 0 0184 2004 l2alloc1 l2 allocation register 1 0184 2008 l2alloc2 l2 allocation register 2 0184 200c l2alloc3 l2 allocation register 3 0184 2010 ? 0184 3ffc ? reserved 0184 4000 l2fbar l2 flush base address register 0184 4004 l2fwc l2 flush word count register 0184 4010 l2cbar l2 clean base address register 0184 4014 l2cwc l2 clean word count register 0184 4020 l1pfbar l1p flush base address register 0184 4024 l1pfwc l1p flush word count register 0184 4030 l1dfbar l1d flush base address register 0184 4034 l1dfwc l1d flush word count register 0184 4038 ? 0184 4ffc ? reserved 0184 5000 l2flush l2 flush register 0184 5004 l2clean l2 clean register 0184 5008 ? 0184 7ffc ? reserved 0184 8000 ? 0184 817c mar0 to mar95 reserved 0184 8180 mar96 controls emifb ce0 range 6000 0000 ? 60ff ffff 0184 8184 mar97 controls emifb ce0 range 6100 0000 ? 61ff ffff 0184 8188 mar98 controls emifb ce0 range 6200 0000 ? 62ff ffff 0184 818c mar99 controls emifb ce0 range 6300 0000 ? 63ff ffff 0184 8190 mar100 controls emifb ce1 range 6400 0000 ? 64ff ffff 0184 8194 mar101 controls emifb ce1 range 6500 0000 ? 65ff ffff 0184 8198 mar102 controls emifb ce1 range 6600 0000 ? 66ff ffff 0184 819c mar103 controls emifb ce1 range 6700 0000 ? 67ff ffff 0184 81a0 mar104 controls emifb ce2 range 6800 0000 ? 68ff ffff 0184 81a4 mar105 controls emifb ce2 range 6900 0000 ? 69ff ffff 0184 81a8 mar106 controls emifb ce2 range 6a00 0000 ? 6aff ffff 0184 81ac mar107 controls emifb ce2 range 6b00 0000 ? 6bff ffff 0184 81b0 mar108 controls emifb ce3 range 6c00 0000 ? 6cff ffff 0184 81b4 mar109 controls emifb ce3 range 6d00 0000 ? 6dff ffff 0184 81b8 mar110 controls emifb ce3 range 6e00 0000 ? 6eff ffff 0184 81bc mar111 controls emifb ce3 range 6f00 0000 ? 6fff ffff 0184 81c0 ? 0184 81fc mar112 to mar127 reserved 0184 8200 mar128 controls emifa ce0 range 8000 0000 ? 80ff ffff 0184 8204 mar129 controls emifa ce0 range 8100 0000 ? 81ff ffff
sgus050a ? january 2004 ? revised march 2004 15 post office box 1443 ? houston, texas 77251?1443 table 6. l2 cache registers (continued) hex address range comments register name acronym 0184 8208 mar130 controls emifa ce0 range 8200 0000 ? 82ff ffff 0184 820c mar131 controls emifa ce0 range 8300 0000 ? 83ff ffff 0184 8210 mar132 controls emifa ce0 range 8400 0000 ? 84ff ffff 0184 8214 mar133 controls emifa ce0 range 8500 0000 ? 85ff ffff 0184 8218 mar134 controls emifa ce0 range 8600 0000 ? 86ff ffff 0184 821c mar135 controls emifa ce0 range 8700 0000 ? 87ff ffff 0184 8220 mar136 controls emifa ce0 range 8800 0000 ? 88ff ffff 0184 8224 mar137 controls emifa ce0 range 8900 0000 ? 89ff ffff 0184 8228 mar138 controls emifa ce0 range 8a00 0000 ? 8aff ffff 0184 822c mar139 controls emifa ce0 range 8b00 0000 ? 8bff ffff 0184 8230 mar140 controls emifa ce0 range 8c00 0000 ? 8cff ffff 0184 8234 mar141 controls emifa ce0 range 8d00 0000 ? 8dff ffff 0184 8238 mar142 controls emifa ce0 range 8e00 0000 ? 8eff ffff 0184 823c mar143 controls emifa ce0 range 8f00 0000 ? 8fff ffff 0184 8240 mar144 controls emifa ce1 range 9000 0000 ? 90ff ffff 0184 8244 mar145 controls emifa ce1 range 9100 0000 ? 91ff ffff 0184 8248 mar146 controls emifa ce1 range 9200 0000 ? 92ff ffff 0184 824c mar147 controls emifa ce1 range 9300 0000 ? 93ff ffff 0184 8250 mar148 controls emifa ce1 range 9400 0000 ? 94ff ffff 0184 8254 mar149 controls emifa ce1 range 9500 0000 ? 95ff ffff 0184 8258 mar150 controls emifa ce1 range 9600 0000 ? 96ff ffff 0184 825c mar151 controls emifa ce1 range 9700 0000 ? 97ff ffff 0184 8260 mar152 controls emifa ce1 range 9800 0000 ? 98ff ffff 0184 8264 mar153 controls emifa ce1 range 9900 0000 ? 99ff ffff 0184 8268 mar154 controls emifa ce1 range 9a00 0000 ? 9aff ffff 0184 826c mar155 controls emifa ce1 range 9b00 0000 ? 9bff ffff 0184 8270 mar156 controls emifa ce1 range 9c00 0000 ? 9cff ffff 0184 8274 mar157 controls emifa ce1 range 9d00 0000 ? 9dff ffff 0184 8278 mar158 controls emifa ce1 range 9e00 0000 ? 9eff ffff 0184 827c mar159 controls emifa ce1 range 9f00 0000 ? 9fff ffff 0184 8280 mar160 controls emifa ce2 range a000 0000 ? a0ff ffff 0184 8284 mar161 controls emifa ce2 range a100 0000 ? a1ff ffff 0184 8288 mar162 controls emifa ce2 range a200 0000 ? a2ff ffff 0184 828c mar163 controls emifa ce2 range a300 0000 ? a3ff ffff 0184 8290 mar164 controls emifa ce2 range a400 0000 ? a4ff ffff 0184 8294 mar165 controls emifa ce2 range a500 0000 ? a5ff ffff 0184 8298 mar166 controls emifa ce2 range a600 0000 ? a6ff ffff 0184 829c mar167 controls emifa ce2 range a700 0000 ? a7ff ffff 0184 82a0 mar168 controls emifa ce2 range a800 0000 ? a8ff ffff 0184 82a4 mar169 controls emifa ce2 range a900 0000 ? a9ff ffff 0184 82a8 mar170 controls emifa ce2 range aa00 0000 ? aaff ffff 0184 82ac mar171 controls emifa ce2 range ab00 0000 ? abff ffff 0184 82b0 mar172 controls emifa ce2 range ac00 0000 ? acff ffff 0184 82b4 mar173 controls emifa ce2 range ad00 0000 ? adff ffff
sgus050a ? january 2004 ? revised march 2004 16 post office box 1443 ? houston, texas 77251?1443 table 6. l2 cache registers (continued) hex address range comments register name acronym 0184 82b8 mar174 controls emifa ce2 range ae00 0000 ? aeff ffff 0184 82bc mar175 controls emifa ce2 range af00 0000 ? afff ffff 0184 82c0 mar176 controls emifa ce3 range b000 0000 ? b0ff ffff 0184 82c4 mar177 controls emifa ce3 range b100 0000 ? b1ff ffff 0184 82c8 mar178 controls emifa ce3 range b200 0000 ? b2ff ffff 0184 82cc mar179 controls emifa ce3 range b300 0000 ? b3ff ffff 0184 82d0 mar180 controls emifa ce3 range b400 0000 ? b4ff ffff 0184 82d4 mar181 controls emifa ce3 range b500 0000 ? b5ff ffff 0184 82d8 mar182 controls emifa ce3 range b600 0000 ? b6ff ffff 0184 82dc mar183 controls emifa ce3 range b700 0000 ? b7ff ffff 0184 82e0 mar184 controls emifa ce3 range b800 0000 ? b8ff ffff 0184 82e4 mar185 controls emifa ce3 range b900 0000 ? b9ff ffff 0184 82e8 mar186 controls emifa ce3 range ba00 0000 ? baff ffff 0184 82ec mar187 controls emifa ce3 range bb00 0000 ? bbff ffff 0184 82f0 mar188 controls emifa ce3 range bc00 0000 ? bcff ffff 0184 82f4 mar189 controls emifa ce3 range bd00 0000 ? bdff ffff 0184 82f8 mar190 controls emifa ce3 range be00 0000 ? beff ffff 0184 82fc mar191 controls emifa ce3 range bf00 0000 ? bfff ffff 0184 8300 ? 0184 83fc mar192 to mar255 reserved 0184 8400 ? 0187 ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 17 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 7. edma registers hex address range acronym register name 01a0 ff9c eprh event polarity high register 01a0 ffa4 ciprh channel interrupt pending high register 01a0 ffa8 cierh channel interrupt enable high register 01a0 ffac ccerh channel chain enable high register 01a0 ffb0 erh event high register 01a0 ffb4 eerh event enable high register 01a0 ffb8 ecrh event clear high register 01a0 ffbc esrh event set high register 01a0 ffc0 pqar0 priority queue allocation register 0 01a0 ffc4 pqar1 priority queue allocation register 1 01a0 ffc8 pqar2 priority queue allocation register 2 01a0 ffcc pqar3 priority queue allocation register 3 01a0 ffdc eprl event polarity low register 01a0 ffe0 pqsr priority queue status register 01a0 ffe4 ciprl channel interrupt pending low register 01a0 ffe8 cierl channel interrupt enable low register 01a0 ffec ccerl channel chain enable low register 01a0 fff0 erl event low register 01a0 fff4 eerl event enable low register 01a0 fff8 ecrl event clear low register 01a0 fffc esrl event set low register 01a1 0000 ? 01a3 ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 18 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 8. edma parameter ram ? hex address range acronym register name comments 01a0 0000 ? 01a0 0017 ? parameters for event 0 (6 words) 01a0 0018 ? 01a0 002f ? parameters for event 1 (6 words) 01a0 0030 ? 01a0 0047 ? parameters for event 2 (6 words) 01a0 0048 ? 01a0 005f ? parameters for event 3 (6 words) 01a0 0060 ? 01a0 0077 ? parameters for event 4 (6 words) 01a0 0078 ? 01a0 008f ? parameters for event 5 (6 words) 01a0 0090 ? 01a0 00a7 ? parameters for event 6 (6 words) 01a0 00a8 ? 01a0 00bf ? parameters for event 7 (6 words) 01a0 00c0 ? 01a0 00d7 ? parameters for event 8 (6 words) 01a0 00d8 ? 01a0 00ef ? parameters for event 9 (6 words) 01a0 00f0 ? 01a0 00107 ? parameters for event 10 (6 words) 01a0 0108 ? 01a0 011f ? parameters for event 11 (6 words) 01a0 0120 ? 01a0 0137 ? parameters for event 12 (6 words) 01a0 0138 ? 01a0 014f ? parameters for event 13 (6 words) 01a0 0150 ? 01a0 0167 ? parameters for event 14 (6 words) 01a0 0168 ? 01a0 017f ? parameters for event 15 (6 words) 01a0 0150 ? 01a0 0167 ? parameters for event 16 (6 words) 01a0 0168 ? 01a0 017f ? parameters for event 17 (6 words) ... ... ... ... 01a0 05d0 ? 01a0 05e7 ? parameters for event 62 (6 words) 01a0 05e8 ? 01a0 05ff ? parameters for event 63 (6 words) 01a0 0600 ? 01a0 0617 ? reload/link parameters for event m (6 words) 01a0 0618 ? 01a0 062f ? reload/link parameters for event n (6 words) ... ... 01a0 07e0 ? 01a0 07f7 ? reload/link parameters for event z (6 words) 01a0 07f8 ? 01a0 07ff ? scratch pad area (2 words) ? the c64x device has twenty-one parameter sets [six (6) words each] that can be used to reload/link edma transfers. table 9. quick dma (qdma) and pseudo registers hex address range acronym register name 0200 0000 qopt qdma options parameter register 0200 0004 qsrc qdma source address register 0200 0008 qcnt qdma frame count register 0200 000c qdst qdma destination address register 0200 0010 qidx qdma index register 0200 0014 ? 0200 001c reserved 0200 0020 qsopt qdma pseudo options register 0200 0024 qssrc qdma pseudo source address register 0200 0028 qscnt qdma pseudo frame count register 0200 002c qsdst qdma pseudo destination address register 0200 0030 qsidx qdma pseudo index register
sgus050a ? january 2004 ? revised march 2004 19 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 10. interrupt selector registers hex address range acronym register name comments 019c 0000 muxh interrupt multiplexer high selects which interrupts drive cpu interrupts 10?15 (int10?int15) 019c 0004 muxl interrupt multiplexer low selects which interrupts drive cpu interrupts 4?9 (int04?int09) 019c 0008 extpol external interrupt polarity sets the polarity of the external interrupts (ext_int4?ext_int7) 019c 000c ? 019c 01ff ? reserved table 11. mcbsp 0 registers hex address range acronym register name comments 018c 0000 drr0 mcbsp0 data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 0x3000 0000 ? 0x33ff ffff drr0 mcbsp0 data receive register via peripheral bus 018c 0004 dxr0 mcbsp0 data transmit register via configuration bus 0x3000 0000 ? 0x33ff ffff dxr0 mcbsp0 data transmit register via peripheral bus 018c 0008 spcr0 mcbsp0 serial port control register 018c 000c rcr0 mcbsp0 receive control register 018c 0010 xcr0 mcbsp0 transmit control register 018c 0014 srgr0 mcbsp0 sample rate generator register 018c 0018 mcr0 mcbsp0 multichannel control register 018c 001c rcere00 mcbsp0 enhanced receive channel enable register 0 018c 0020 xcere00 mcbsp0 enhanced transmit channel enable register 0 018c 0024 pcr0 mcbsp0 pin control register 018c 0028 rcere10 mcbsp0 enhanced receive channel enable register 1 018c 002c xcere10 mcbsp0 enhanced transmit channel enable register 1 018c 0030 rcere20 mcbsp0 enhanced receive channel enable register 2 018c 0034 xcere20 mcbsp0 enhanced transmit channel enable register 2 018c 0038 rcere30 mcbsp0 enhanced receive channel enable register 3 018c 003c xcere30 mcbsp0 enhanced transmit channel enable register 3 018c 0040 ? 018f ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 20 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 12. mcbsp 1 registers hex address range acronym register name comments 0190 0000 drr1 mcbsp1 data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 0x3400 0000 ? 0x37ff ffff drr1 mcbsp1 data receive register via peripheral bus 0190 0004 dxr1 mcbsp1 data transmit register via configuration bus 0x3400 0000 ? 0x37ff ffff dxr1 mcbsp1 data transmit register via peripheral bus 0190 0008 spcr1 mcbsp1 serial port control register 0190 000c rcr1 mcbsp1 receive control register 0190 0010 xcr1 mcbsp1 transmit control register 0190 0014 srgr1 mcbsp1 sample rate generator register 0190 0018 mcr1 mcbsp1 multichannel control register 0190 001c rcere01 mcbsp1 enhanced receive channel enable register 0 0190 0020 xcere01 mcbsp1 enhanced transmit channel enable register 0 0190 0024 pcr1 mcbsp1 pin control register 0190 0028 rcere11 mcbsp1 enhanced receive channel enable register 1 0190 002c xcere11 mcbsp1 enhanced transmit channel enable register 1 0190 0030 rcere21 mcbsp1 enhanced receive channel enable register 2 0190 0034 xcere21 mcbsp1 enhanced transmit channel enable register 2 0190 0038 rcere31 mcbsp1 enhanced receive channel enable register 3 0190 003c xcere31 mcbsp1 enhanced transmit channel enable register 3 0190 0040 ? 0193 ffff ? reserved table 13. mcbsp 2 registers hex address range acronym register name comments 01a4 0000 drr2 mcbsp2 data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 0x3800 0000 ? 0x3bff ffff drr2 mcbsp2 data receive register via peripheral bus 01a4 0004 dxr2 mcbsp2 data transmit register via configuration bus 0x3800 0000 ? 0x3bff ffff dxr2 mcbsp2 data transmit register via peripheral bus 01a4 0008 spcr2 mcbsp2 serial port control register 01a4 000c rcr2 mcbsp2 receive control register 01a4 0010 xcr2 mcbsp2 transmit control register 01a4 0014 srgr2 mcbsp2 sample rate generator register 01a4 0018 mcr2 mcbsp2 multichannel control register 01a4 001c rcere02 mcbsp2 enhanced receive channel enable register 0 01a4 0020 xcere02 mcbsp2 enhanced transmit channel enable register 0 01a4 0024 pcr2 mcbsp2 pin control register 01a4 0028 rcere12 mcbsp2 enhanced receive channel enable register 1 01a4 002c xcere12 mcbsp2 enhanced transmit channel enable register 1 01a4 0030 rcere22 mcbsp2 enhanced receive channel enable register 2 01a4 0034 xcere22 mcbsp2 enhanced transmit channel enable register 2 01a4 0038 rcere32 mcbsp2 enhanced receive channel enable register 3 01a4 003c xcere32 mcbsp2 enhanced transmit channel enable register 3 01a4 0040 ? 01a7 ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 21 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 14. timer 0 registers hex address range acronym register name comments 0194 0000 ctl0 timer 0 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0194 0004 prd0 timer 0 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0194 0008 cnt0 timer 0 counter register contains the current value of the incrementing counter. 0194 000c ? 0197 ffff ? reserved table 15. timer 1 registers hex address range acronym register name comments 0198 0000 ctl1 timer 1 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0198 0004 prd1 timer 1 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0198 0008 cnt1 timer 1 counter register contains the current value of the incrementing counter. 0198 000c ? 019b ffff ? reserved table 16. timer 2 registers hex address range acronym register name comments 01ac 0000 ctl2 timer 2 control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 01ac 0004 prd2 timer 2 period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 01ac 0008 cnt2 timer 2 counter register contains the current value of the incrementing counter. 01ac 000c ? 01af ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 22 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 17. hpi registers hex address range acronym register name comments ? hpid hpi data register host read/write access only 0188 0000 hpic hpi control register hpic has both host/cpu read/write access 0188 0004 hpia (hpiaw) ? hpi address register (write) hpia has both host/cpu 0188 0008 hpia (hpiar) ? hpi address register (read) hpia has both host/cpu read/write access 0188 000c ? 0189 ffff ? reserved 018a 0000 trctl hpi transfer request control register 018a 0004 ? 018b ffff ? reserved ? host access to the hpia register updates both the hpiaw and hpiar registers. the cpu can access hpiaw and hpiar independently. table 18. gpio registers hex address range acronym register name 01b0 0000 gpen gpio enable register 01b0 0004 gpdir gpio direction register 01b0 0008 gpval gpio value register 01b0 000c ? reserved 01b0 0010 gpdh gpio delta high register 01b0 0014 gphm gpio high mask register 01b0 0018 gpdl gpio delta low register 01b0 001c gplm gpio low mask register 01b0 0020 gpgc gpio global control register 01b0 0024 gppol gpio interrupt polarity register 01b0 0028 ? 01b0 01ff ? reserved 01b0 0200 device_rev silicon revision identification register (for more details, see the device characteristics listed in table 1.) 01b0 0204 ? 01b3 ffff ? reserved
sgus050a ? january 2004 ? revised march 2004 23 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 19. pci peripheral registers (c6415 and c6416 only) ? hex address range acronym register name 01c0 0000 rstsrc dsp reset source/status register 01c0 0004 ? reserved 01c0 0008 pciis pci interrupt source register 01c0 000c pciien pci interrupt enable register 01c0 0010 dspma dsp master address register 01c0 0014 pcima pci master address register 01c0 0018 pcimc pci master control register 01c0 001c cdspa current dsp address register 01c0 0020 cpcia current pci address register 01c0 0024 ccnt current byte count register 01c0 0028 ? reserved 01c0 002c ? 01c1 ffef ? reserved 0x01c1 fff0 hsr host status register 0x01c1 fff4 hdcr host-to-dsp control register 0x01c1 fff8 dspp dsp page register 0x01c1 fffc ? reserved 01c2 0000 eeadd eeprom address register 01c2 0004 eedat eeprom data register 01c2 0008 eectl eeprom control register 01c2 000c ? 01c2 ffff ? reserved 01c3 0000 trctl pci transfer request control register 01c3 0004 ? 01c3 ffff ? reserved ? these pci registers are not supported on the c6414 device.
sgus050a ? january 2004 ? revised march 2004 24 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 20. utopia (c6415 and c6416 only) ? hex address range acronym register name 01b4 0000 ucr utopia control register 01b4 0004 ? reserved 01b4 0008 ? reserved 01b4 000c uier utopia interrupt enable register 01b4 0010 uipr utopia interrupt pending register 01b4 0014 cdr clock detect register 01b4 0018 eier error interrupt enable register 01b4 001c eipr error interrupt pending register 01b4 0020 ? 01b7 ffff ? reserved ? these utopia registers are not supported on the c6414 device. table 21. utopia queues (c6415 and c6416 only) ? hex address range acronym register name 3c00 0000 urq utopia receive queue 3d00 0000 uxq utopia transmit queue 3d00 0004 ? 3fff ffff ? reserved ? these utopia registers are not supported on the c6414 device.
sgus050a ? january 2004 ? revised march 2004 25 post office box 1443 ? houston, texas 77251?1443 peripheral register descriptions (continued) table 22. vcp registers (c6416 only) ? edma bus hex address range peripheral bus hex address range acronym register name 5000 0000 01b8 0000 vcpic0 vcp input configuration register 0 5000 0004 01b8 0004 vcpic1 vcp input configuration register 1 5000 0008 01b8 0008 vcpic2 vcp input configuration register 2 5000 000c 01b8 000c vcpic3 vcp input configuration register 3 5000 0010 01b8 0010 vcpic4 vcp input configuration register 4 5000 0014 01b8 0014 vcpic5 vcp input configuration register 5 5000 0040 01b8 0024 vcpout0 vcp output register 0 5000 0044 01b8 0028 vcpout1 vcp output register 1 5000 0080 ? vcpwbm vcp branch metrics write register 5000 0088 ? vcprdecs vcp decisions read register ? 01b8 0018 vcpexe vcp execution register ? 01b8 0020 vcpend vcp endian register ? 01b8 0040 vcpstat0 vcp status register 0 ? 01b8 0044 vcpstat1 vcp status register 1 ? 01b8 0050 vcperr vcp error register ? these vcp registers are supported on the c6416 device only. table 23. tcp registers (c6416 only) ? edma bus hex address range peripheral bus hex address range acronym register name 5800 0000 01ba 0000 tcpic0 tcp input configuration register 0 5800 0004 01ba 0004 tcpic1 tcp input configuration register 1 5800 0008 01ba 0008 tcpic2 tcp input configuration register 2 5800 000c 01ba 000c tcpic3 tcp input configuration register 3 5800 0010 01ba 0010 tcpic4 tcp input configuration register 4 5800 0014 01ba 0014 tcpic5 tcp input configuration register 5 5800 0018 01ba 0018 tcpic6 tcp input configuration register 6 5800 001c 01ba 001c tcpic7 tcp input configuration register 7 5800 0020 01ba 0020 tcpic8 tcp input configuration register 8 5800 0024 01ba 0024 tcpic9 tcp input configuration register 9 5800 0028 01ba 0028 tcpic10 tcp input configuration register 10 5800 002c 01ba 002c tcpic11 tcp input configuration register 11 5800 0030 01ba 0030 tcpout tcp output parameters register 5802 0000 ? tcpsp tcp systematics and parities memory 5804 0000 ? tcpext tcp extrinsic memory 5806 0000 ? tcpap tcp apriori memory 5808 0000 ? tcpinter tcp interleaver memory 580a 0000 ? tcphd tcp hard decisions memory ? 01ba 0038 tcpexe tcp execution register ? 01ba 0040 tcpend tcp endian register ? 01ba 0050 tcperr tcp error register ? 01ba 0058 tcpstat tcp status register ? these tcp registers are supported on the c6416 device only.
sgus050a ? january 2004 ? revised march 2004 26 post office box 1443 ? houston, texas 77251?1443 edma channel synchronization events the c64x edma supports up to 64 edma channels which service peripheral devices and external memory. table 24 lists the source of c64x edma synchronization events associated with each of the programmable edma channels. for the c64x device, the association of an event to a channel is fixed; each of the edma channels has one specific event associated with it. these specific events are captured in the edma event registers (erl, erh) even if the events are disabled by the edma event enable registers (eerl, eerh). the priority of each event can be specified independently in the transfer parameters stored in the edma parameter ram. for more detailed information on the edma module and how edma events are enabled, captured, processed, linked, chained, and cleared, etc., see the tms320c6000 dsp enhanced direct memory access (edma) controller reference guide (literature number spru234).
sgus050a ? january 2004 ? revised march 2004 27 post office box 1443 ? houston, texas 77251?1443 edma channel synchronization events (continued) table 24. smj320c64x edma channel synchronization events ? edma channel event name event description 0 dsp_int hpi/pci-to-dsp interrupt (pci peripheral supported on c6415 and c6416 only) ? 1 tint0 timer 0 interrupt 2 tint1 timer 1 interrupt 3 sd_inta emifa sdram timer interrupt 4 gpint4/ext_int4 gpio event 4/external interrupt pin 4 5 gpint5/ext_int5 gpio event 5/external interrupt pin 5 6 gpint6/ext_int6 gpio event 6/external interrupt pin 6 7 gpint7/ext_int7 gpio event 7/external interrupt pin 7 8 gpint0 gpio event 0 9 gpint1 gpio event 1 10 gpint2 gpio event 2 11 gpint3 gpio event 3 12 xevt0 mcbsp0 transmit event 13 revt0 mcbsp0 receive event 14 xevt1 mcbsp1 transmit event 15 revt1 mcbsp1 receive event 16 ? none 17 xevt2 mcbsp2 transmit event 18 revt2 mcbsp2 receive event 19 tint2 timer 2 interrupt 20 sd_intb emifb sdram timer interrupt 21 ? reserved, for future expansion 22?27 ? none 28 vcprevt vcp receive event (c6416 only) 29 vcpxevt vcp transmit event (c6416 only) 30 tcprevt tcp receive event (c6416 only) 31 tcpxevt tcp transmit event (c6416 only) 32 urevt utopia receive event (c6415 and c6416 only) ? 33?39 ? none 40 uxevt utopia transmit event (c6415 and c6416 only) ? 41?47 ? none 48 gpint8 gpio event 8 49 gpint9 gpio event 9 50 gpint10 gpio event 10 51 gpint11 gpio event 11 52 gpint12 gpio event 12 53 gpint13 gpio event 13 54 gpint14 gpio event 14 55 gpint15 gpio event 15 56?63 ? none ? in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the tms320c6000 dsp enhanced direct memory access (edma) controller reference guide (literature number spru234). ? the pci and utopia peripherals are not supported on the c6414 device; therefore, these edma synchronization events are reserved . the vcp/tcp edma synchronization events are supported on the c6416 only. for the c6414 and c6415 devices, these events are rese rved.
sgus050a ? january 2004 ? revised march 2004 28 post office box 1443 ? houston, texas 77251?1443 interrupt sources and interrupt selector the c64x dsp core supports 16 prioritized interrupts, which are listed in table 25. the highest-priority interrupt is int_00 (dedicated to reset) while the lowest-priority interrupt is int_15. the first four interrupts (int_00?int_03) are non-maskable and fixed. the remaining interrupts (int_04?int_15) are maskable and default to the interrupt source specified in table 25. the interrupt source for interrupts 4?15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the interrupt selector control registers: muxh (address 0x019c0000) and muxl (address 0x019c0004).
sgus050a ? january 2004 ? revised march 2004 29 post office box 1443 ? houston, texas 77251?1443 interrupt sources and interrupt selector (continued) table 25. c64x dsp interrupts cpu interrupt number interrupt selector control register selector value (binary) interrupt event interrupt source int_00 ? ? ? reset int_01 ? ? ? nmi int_02 ? ? ? reserved reserved. do not use. int_03 ? ? ? reserved reserved. do not use. int_04 ? muxl[4:0] 00100 gpint4/ext_int4 gpio interrupt 4/external interrupt pin 4 int_05 ? muxl[9:5] 00101 gpint5/ext_int5 gpio interrupt 5/external interrupt pin 5 int_06 ? muxl[14:10] 00110 gpint6/ext_int6 gpio interrupt 6/external interrupt pin 6 int_07 ? muxl[20:16] 00111 gpint7/ext_int7 gpio interrupt 7/external interrupt pin 7 int_08 ? muxl[25:21] 01000 edma_int edma channel (0 through 63) interrupt int_09 ? muxl[30:26] 01001 emu_dtdma emu dtdma int_10 ? muxh[4:0] 00011 sd_inta emifa sdram timer interrupt int_11 ? muxh[9:5] 01010 emu_rtdxrx emu real-time data exchange (rtdx) receive int_12 ? muxh[14:10] 01011 emu_rtdxtx emu rtdx transmit int_13 ? muxh[20:16] 00000 dsp_int hpi/pci-to-dsp interrupt (pci supported on c6415 and c6416 only) int_14 ? muxh[25:21] 00001 tint0 timer 0 interrupt int_15 ? muxh[30:26] 00010 tint1 timer 1 interrupt ? ? 01100 xint0 mcbsp0 transmit interrupt ? ? 01101 rint0 mcbsp0 receive interrupt ? ? 01110 xint1 mcbsp1 transmit interrupt ? ? 01111 rint1 mcbsp1 receive interrupt ? ? 10000 gpint0 gpio interrupt 0 ? ? 10001 xint2 mcbsp2 transmit interrupt ? ? 10010 rint2 mcbsp2 receive interrupt ? ? 10011 tint2 timer 2 interrupt ? ? 10100 sd_intb emifb sdram timer interrupt ? ? 10101 reserved reserved. do not use. ? ? 10110 reserved reserved. do not use. ? ? 10111 uint utopia interrupt (c6415/c6416 only) ? ? 11000 ? 11101 reserved reserved. do not use. ? ? 11110 vcpint vcp interrupt (c6416 only) ? ? 11111 tcpint tcp interrupt (c6416 only) ? interrupts int_00 through int_03 are non-maskable and fixed. ? interrupts int_04 through int_15 are programmable by modifying the binary selector values in the interrupt selector control registers fields. table 25 shows the default interrupt sources for interrupts int_04 through int_15. for more detailed information on interrupt sources and selection, see the tms320c6000 dsp interrupt selector reference guide (literature number spru646).
sgus050a ? january 2004 ? revised march 2004 30 post office box 1443 ? houston, texas 77251?1443 signal groups description trst gp7/ext_int7 ? ieee standard 1149.1 (jtag) emulation reserved reset and interrupts control/status tdi tdo tms tck emu0 emu1 nmi gp6/ext_int6 ? gp5/ext_int5 ? gp4/ext_int4 ? reset rsv rsv rsv rsv clock/pll clkin clkmode1 clkmode0 pllv emu2 emu3 emu4 emu5 rsv gpio general-purpose input/output (gpio) port gp7/ext_int7 ? gp6/ext_int6 ? gp5/ext_int5 ? gp4/ext_int4 ? gp3 clkout6/gp2 ? clkout4/gp1 ? gp0 clkout6/gp2 ? clkout4/gp1 ? emu6 emu7 emu8 emu9 emu10 gp15/prst gp14/pclk gp13/pinta gp12/pgnt gp11/preq gp10/pcbe3 gp9/pidsel clks2/gp8 ? these pins are muxed with the gpio port pins and by default these signals function as clocks (clkout4 or clkout6) or mcbsp2 clock source (clks2). to use these muxed pins as gpio signals, the appropriate gpio register bits (gpxen and gpxdir) must be properly enabled and configured. for more details, see the device configurations section of this data sheet. ? these pins are gpio pins that can also function as external interrupt sources (ext_int[7:4]). default after reset is ext_intx o r gpio as input-only. ? rsv emu11 rsv rsv rsv ? ? ? peripheral control/status pci_en mcbsp2_en for the c6415 and c6416 devices, these gpio pins are muxed with the pci peripheral pins. by default, these signals are set up t o no function with both the gpio and pci pin functions disabled . for more details on these muxed pins, see the device configurations section of this data sheet. for the c6414 device, the gpio peripheral pins are not muxed; the c6414 device does not support the pci peripheral. figure 2. cpu and peripheral signals
sgus050a ? january 2004 ? revised march 2004 31 post office box 1443 ? houston, texas 77251?1443 signal groups description (continued) ace3 aeclkout1 aed[63:0] ace2 ace1 ace0 aea[22:3] abe7 abe6 abe5 abe4 aardy data memory map space select address byte enables 64 20 external memory i/f control emifa (64-bit) ? aeclkin ahold aholda abusreq bus arbitration aare /asdcas /asads /asr e asdcke aeclkout2 asoe3 abe3 abe2 abe1 abe0 bce3 bed[15:0] bce2 bce1 bce0 bea[20:1] data memory map space select address byte enables 16 external memory i/f control beclkin bhold bholda bbusreq bus arbitration bsoe3 bbe1 bbe0 emifb (16-bit) ? beclkout1 bardy beclkout2 aaoe /asdras /asoe aawe /asdwe /aswe bare /bsdcas /bsads /bsr e baoe /bsdras /bsoe bawe /bsdwe /bswe bpdt apdt ? these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa signal whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this doc ument, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. 20 figure 3. peripheral signals
sgus050a ? january 2004 ? revised march 2004 32 post office box 1443 ? houston, texas 77251?1443 signal groups description (continued) hhwil/ptrdy hcntl0/pstop hcntl1/pdevsel data register select half-word select control hpi ? (host-port interface) 32 hd[31:0]/ad[31:0] has /ppar hr/w /pcbe2 hcs /pperr hds1 /pserr hds2 /pcbe1 hrdy /pirdy hint /pframe (hpi16 only) ? for the c6415 and c6416 devices, these hpi pins are muxed with the pci peripheral. by default, these signals function as hpi. f or more details on these muxed pins, see the device configurations section of this data sheet. for the c6414 device, these hpi pins are not muxed; the c6414 device does not support the pci peripheral. ? for the c6415 and c6416 devices, these pci pins (excluding pcbe0 and xsp_cs) are muxed with the hpi, mcbsp2, or gpio peripherals. by default, these signals function as hpi, mcbsp2, and no function, respectively. for more details on these muxed pins, see the device configurations section of this data sheet. for the c6414 device, the hpi, mcbsp2, and gpio peripheral pins are not muxed; the c6414 device does not support the pci peripheral. for the c6414 device, these pins are ?reserved (leave unconnected, do not connect to power or ground).? hd[31:0]/ad[31:0] hr/w /pcbe2 hds2 /pcbe1 pcbe0 gp12/pgnt gp11/preq gp14/pclk hint /pframe gp13/pinta data/address arbitration 32 clock control pci interface ? (c6415 and c6416 only) has /ppar gp15/prst hrdy /pirdy hcntl0/pstop hhwil/ptrdy gp10/pcbe3 gp9/pidsel hcntl1/pdevsel hds1 /pserr error command byte enable serial eeprom dx2/xsp_do xsp_cs clkx2/xsp_clk dr2/xsp_di hcs /pperr figure 3. peripheral signals (continued)
sgus050a ? january 2004 ? revised march 2004 33 post office box 1443 ? houston, texas 77251?1443 signal groups description (continued) mcbsps (multichannel buffered serial ports) clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 transmit mcbsp0 receive clock clkx1/uraddr4 ? fsx1/uxaddr3 ? dx1/uxaddr4 ? clkr1/uraddr2 ? fsr1/uxaddr2 ? dr1/uxaddr1 ? clks1/uraddr3 ? transmit mcbsp1 receive clock clkx2/xsp_clk ? fsx2 dx2/xsp_do ? clkr2 fsr2 dr2/xsp_di ? clks2/gp8 ? transmit mcbsp2 receive clock ? for the c6415 and c6416 devices, these mcbsp2 and mcbsp1 pins are muxed with the pci and utopia peripherals, respectively. by default, these signals function as mcbsp2 and mcbsp1, respectively. for more details on these muxed pins, see the device configurations section of this data sheet. for the c6414 device, these mcbsp2 and mcbsp1 peripheral pins are not muxed; the c6414 device does not support pci and utopia peripherals. ? the mcbsp2 clock source pin (clks2, default) is muxed with the gp8 pin. to use this muxed pin as the gp8 signal, the appropriat e gpio register bits (gp8en and gp8dir) must be properly enabled and configured. for more details, see the device configurations section of this data sheet. figure 3. peripheral signals (continued)
sgus050a ? january 2004 ? revised march 2004 34 post office box 1443 ? houston, texas 77251?1443 signal groups description (continued) clkr1/uraddr2 ? control/status clkx1/uraddr4 ? urdata0 urdata1 clks1/uraddr3 ? uraddr1 uraddr0 receive urdata7 urdata4 urdata3 urdata2 urclav urenb urdata5 urdata6 ursoc urclk clock control/status transmit clock fsr1/uxaddr2 ? dx1/uxaddr4 ? uxdata0 uxdata1 fsx1/uxaddr3 ? dr1/uxaddr1 ? uxaddr0 uxdata7 uxdata4 uxdata3 uxdata2 uxclav uxenb uxdata5 uxdata6 uxsoc uxclk utopia (slave) [c6415 and c6416 only] ? for the c6415 and c6416 devices, these utopia pins are muxed with the mcbsp1 peripheral. by default, these signals function as mcbsp1. for more details on these muxed pins, see the device configurations section of this data sheet. for the c6414 device, these mcbsp1 peripheral pins are not muxed; the c6414 does not support the utopia peripheral. tout0 timers tinp0 tout1 timer 1 tinp1 tout2 timer 2 tinp2 timer 0 figure 3. peripheral signals (continued)
sgus050a ? january 2004 ? revised march 2004 35 post office box 1443 ? houston, texas 77251?1443 device configurations the c6414, c6415, and c6416 peripheral selections and other device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset): peripherals selection (c6415 and c6416 devices) ? bea11 (utopia_en) ? pci_en (for c6415 or c6416, see table 27 footnotes) ? mcbsp2_en (for c6414 or c6416, see table 27 footnotes) the c6414 device does not support the pci and utopia peripherals; for proper operation of the c6414 device, do not oppose the internal pulldowns (ipds) on the bea11, pci_en, and mcbsp2_en pins. (for ipus/ipds on pins, see the terminal functions table of this data sheet.) other device configurations (c64x) ? bea[20:13, 7] ? hd5 peripherals selection some c6415/c6416 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., hpi, general-purpose input/output pins gp[15:9], pci and its internal eeprom, mcbsp1, mc bsp2, an d ut opia). the vcp/tcp coprocessors (c6416 only) and other c64x peripherals (i.e., the timers, mcbsp0, and the gp[8:0] pins), are always available. utopia and mcbsp1 peripherals the utopia_en pin (bea11) is latched at reset. for c6415 and c6416 devices, this pin selects whether the utopia peripheral or mcbsp1 peripheral is functionally enabled (see table 26). the c6414 device does not support the ut opia peripheral; for proper device operation, do not oppose the internal pulldown (ipd) on the bea11 pin. table 26. utopia_en peripheral selection (mcbsp1 and utopia) (c6415/c6416 only) peripheral selection peripherals selected utopia_en (bea11) pin [f14] utopia mcbsp1 description 0 mcbsp1 is enabled and utopia is disabled [default]. this means all multiplexed mcbsp1/utopia pins function as mcbsp1 and all other standalone utopia pins are tied-off (hi-z). 1 utopia is enabled and mcbsp1 is disabled. this means all multiplexed mcbsp1/utopia pins now function as utopia and all other standalone mcbsp1 pins are tied-off (hi-z). hpi, gp[15:9], pci, eeprom (internal to pci), and mcbsp2 peripherals the pci_en and mcbsp2_en pins are latched at reset. they determine specific peripheral selection for the c6415 and c6416 devices, summarized in table 27. the c6414 device does not support the pci peripheral; for proper device operation, do not oppose the internal pulldowns (ipds) on the pci_en and mcbsp2_en pins.
sgus050a ? january 2004 ? revised march 2004 36 post office box 1443 ? houston, texas 77251?1443 device configurations (continued) table 27. pci_en and mcbsp2_en peripheral selection (hpi, gp[15:9], pci, and mcbsp2) peripheral selection ? peripherals selected pci_en pin [t8] mcbsp2_en pin [ab4] hpi gp[15:9] pci eeprom (internal to pci) mcbsp2 0 0 0 1 1 0 ? 1 1 ? the pci_en pin must be driven valid at all times and the user must not switch values throughout device operation. the mcbsp2_en pin must be driven valid at all times and the user can switch values throughout device operation. ? the only time mcbsp2 is disabled is when both pci_en = 1 and mcbsp2_en = 0. this configuration enables, at reset, the auto-init ialization of the pci peripheral through the pci internal eeprom [provided the pci eeprom auto-initialization pin (bea13) is pulled up (eeai = 1)]. the user can then enable the mcbsp2 peripheral (disabling eeprom) by dynamically changing mcbsp2_en to a ?1? after the device is initialized (out of reset). ? if the pci is disabled (pci_en = 0), the hpi peripheral is enabled and gp[15:9] pins can be programmed as gpio, provided the gpxen and gpxdir bits are properly configured. this means all multiplexed hpi/pci pins function as hpi and all standalone pci pins (pcbe0 and xsp_cs) are tied-off (hi-z). also, the multiplexed gpio/pci pins can be used as gpio with the proper software configuration of the gpio enable and direction registers (for more details, see table 29). ? if the pci is enabled (pci_en = 1), the hpi peripheral is disabled. this means all multiplexed hpi/pci pins function as pci. also, the multiplexed gpio/pci pins function as pci pins (for more details, see table 29). ? the mcbsp2_en pin, in combination with the pci_en pin, controls the selection of the mcbsp2 peripheral and the pci internal eeprom (for more details, see table 27 and its footnotes). other device configurations table 28 describes the c6414, c6415, and c6416 devices configuration pins, which are set up via external pullup/pulldown resistors through the specified emifb address bus pins (bea[20:13, 11, 9:7]) and the hd5 pin. for more details on these device configuration pins, see the terminal functions table and the debugging considerations section.
sgus050a ? january 2004 ? revised march 2004 37 post office box 1443 ? houston, texas 77251?1443 device configurations (continued) table 28. device configuration pins (bea[20:13, 9:7], hd5, and bea11) configuration pin no. functional description bea20 e15 device endian mode (lend) 0 ? system operates in big endian mode 1 ? system operates in little endian mode (default) bea[19:18] [d17, j14] bootmode [1:0] 00 ? no boot 01 ? hpi boot 10 ? emifb 8-bit rom boot with default timings (default mode) 11 ? reserved bea[17:16] [e16, g15] emifa input clock select clock mode select for emifa (aeclkin_sel[1:0]) 00 ? aeclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate 11 ? reserved bea[15:14] [c18, f15] emifb input clock select clock mode select for emifb (beclkin_sel[1:0]) 00 ? beclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate 11 ? reserved bea13 d16 pci eeprom auto-initialization (eeai) [c6415 and c6416 devices only] [the c6414 device does not support the pci peripheral; for proper device operation, do not oppose the internal pulldown (ipd) on the bea13 pin . ] pci auto-initialization via external eeprom 0 ? pci auto-initialization through eeprom is disabled; the pci peripheral uses the specified pci default values (default). 1 ? pci auto-initialization through eeprom is enabled; the pci peripheral is configured through eeprom provided the pci peripheral pin is enabled (pci_en = 1) and the mcbsp2 peripheral pin is disabled (mcbsp2_en = 0). note: if the pci peripheral is disabled (pci_en pin = 0), this pin must not be pulled up. for more information on the pci eeprom default values, see the tms320c6000 dsp peripheral component interconnect (pci) reference guide (literature number spru581). bea11 f14 utopia enable (utopia_en) [c6415 and c6416 devices only] [the c6414 device does not support the utopia peripheral; for proper device operation, do not oppose the internal pulldown (ipd) on the bea11 pin . ] utopia peripheral enable (functional) 0 ? utopia peripheral disabled (mcbsp1 functions are enabled). [default] this means all multiplexed mcbsp1/utopia pins function as mcbsp1 and all other standalone utopia pins are tied-off (hi-z). 1 ? utopia peripheral enabled (mcbsp1 functions are disabled). this means all multiplexed mcbsp1/utopia pins now function as utopia and all other standalone mcbsp1 pins are tied-off (hi-z).
sgus050a ? january 2004 ? revised march 2004 38 post office box 1443 ? houston, texas 77251?1443 device configurations (continued) table 28. device configuration pins (bea[20:13, 9:7], hd5, and bea11) (continued) configuration pin no. functional description bea7 bea8 bea9 e14 g14 g13 c6414 devices c6415 devices c6416 devices do not oppose internal pulldown (ipd) pullup ? do not oppose ipd do not oppose ipd do not oppose ipd pullup ? do not oppose ipd do not oppose ipd pullup ? ? for proper device operation, this pin must be externally pulled up with a 1-k ? resistor. hd5 u4 hpi peripheral bus width (hpi_width) 0 ? hpi operates as an hpi16. (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins are reserved pins in the hi-z state.) 1 ? hpi operates as an hpi32. (hpi bus is 32 bits wide. all hd[31:0] pins are used for host-port operations.)
sgus050a ? january 2004 ? revised march 2004 39 post office box 1443 ? houston, texas 77251?1443 device configurations (continued) multiplexed pins multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. those muxed pins that are configured by software can be programmed to switch functionalities at any time. those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. table 29 identifies the multiplexed pins on the c6414, c6415, and c6416 devices; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. debugging considerations it is recommended that external connections be provided to device configuration pins, including clkmode[1:0], bea[20:13, 11, 9:7], hd5/ad5, pci_en, and mcbsp2_en. although internal pullup/pulldown resistors exist on these pins (except for h d5/ad5), providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. internal pullup/pulldown resistors also exist on the non-configuration pins on the bea bus (bea[12, 10, 6:1]). do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. if an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. for the internal pullup/pulldown resistors on the c6414, c6415, and c6416 device pins, see the terminal functions table.
sgus050a ? january 2004 ? revised march 2004 40 post office box 1443 ? houston, texas 77251?1443 device configurations (continued) table 29. c6414, c6415, and c6416 device multiplexed pins ? multiplexed pins default function default setting description name no. default function default setting description clkout4/gp1 ? y7 clkout4 gp1en = 0 (disabled) these pins are software-configurable . to use these pins as gpio pins, the gpxen bits in the gpio enable clkout6/gp2 ? t10 clkout6 gp2en = 0 (disabled) gpxen bits in the gpio enable register and the gpxdir bits in the gpio direction register must be properly configured. clks2/gp8 ? w7 clks2 gp8en = 0 (disabled) properly configured. gpxen = 1: gpx pin enabled gpxdir = 0: gpx pin is an input gpxdir = 1: gpx pin is an output gp9/pidsel k6 to use gp[15:9] as gpio pins, the pc i needs to be disabled (pci_en = 0), the gp10/pcbe3 l7 to use gp[15:9] as gpio pins, the pci needs to be disabled (pci_en = 0), the gpxen bits in the gpio enable gp11/preq h6 gpxen = 0 (disabled) gpxen bits in the gpio enable register and the gpxdir bits in the gp12/pgnt j7 none gpxen = 0 (disabled) pci_en = 0 (disabled) ? register and the gpxdir bits in the gpio direction register must be properly configured. gp13/pinta g4 none pci_en = 0 (disabled) ? gpio direction register must be properly configured. gpxen = 1: gpx pin enabled gp14/pclk g5 gpxen = 1: gpx pin enabled gpxdir = 0: gpx pin is an input gp15/prst j8 gpxdir = 0: gpx pin is an input gpxdir = 1: gpx pin is an output dx1/uxaddr4 y10 dx1 fsx1/uxaddr3 aa11 fsx1 by default, mcbsp1 is enabled upon fsr1/uxaddr2 aa8 fsr1 utopia_en (bea11) = 0 by default, mcbsp1 is enabled upon reset (utopia is disabled). to enable the utopia peripheral, an dr1/uxaddr1 v11 dr1 utopia_en (bea11) = 0 (disabled) ? reset (utopia is disabled). to enable the utopia peripheral, an external pullup resistor (1 k ? ) must be clkx1/uraddr4 t12 clkx1 (disabled) ? external pullup resistor (1 k ? ) must be provided on the bea11 pin (setting clks1/uraddr3 y8 clks1 provided on the bea11 pin (setting utopia_en = 1 at reset). clkr1/uraddr2 ab7 clkr1 utopia_en = 1 at reset). clkx2/xsp_clk w5 clkx2 dr2/xsp_di y4 dr2 dx2/xsp_do r9 dx2 hd[31:0]/ad[31:0] hd[31:0] has /ppar n7 has by default, hpi is enabled upon reset hcntl1/pdevsel n8 hcntl1 by default, hpi is enabled upon rese t (pci is disabled). hcntl0/pstop p5 hcntl0 pci_en = 0 (disabled) ? (pci is disabled). to enable the pci peripheral an external hds1 /pserr r5 hds1 pci_en = 0 (disabled) ? to enable the pci peripheral an external pullup resistor (1 k ? ) must be provided on the pci_en pin (setting pci_en = 1 hds2 /pcbe1 p6 hds2 pullup resistor (1 k ) must be provided on the pci_en pin (setting pci_en = 1 at reset). hr/w /pcbe2 n6 hr/w at reset). hwwil/ptrdy n5 hhwil (hpi16 only) hint /pframe p4 hint hcs /pperr n9 hcs hrdy /pirdy n4 hrdy ? for the c6415 and c6416 devices, all other standalone utopia and pci pins are tied-off internally (pins in hi-z) when the perip heral is disabled [utopia_en (bea11) = 0 or pci_en = 0]. ? the c6414 device does not support the pci and utopia peripherals. these are the only multiplexed pins on the c6414 device, all other pins are standalone peripheral functions and are not muxed. for the hd[31:0]/ad[31:0] multiplexed pins pin numbers, see the terminal functions table.
sgus050a ? january 2004 ? revised march 2004 41 post office box 1443 ? houston, texas 77251?1443 terminal functions signal type ? ipd/ ipu ? description name no. type ? ipd/ ipu ? description clock/pll configuration clkin h4 i ipd clock input. this clock is the input to the on-chip pll. clkout4/gp1 y7 i/o/z ipd clock output at 1/4 of the device speed ( o/z ) [default] or this pin can be programmed as a gpio 1 pin ( i/o/z ). clkout6/gp2 t10 i/o/z ipd clock output at 1/6 of the device speed ( o/z ) [default] or this pin can be programmed as a gpio 2 pin ( i/o/z ). clkmode1 k8 i ipd clock mode select ? selects whether the cpu clock frequency = input clock frequency x1 (bypass), x6, or x12. clkmode0 e3 i ipd ? selects whether the cpu clock frequency = input clock frequency x1 (bypass), x6, or x12. for more details on the clkmode pins and the pll multiply factors, see the clock pll section of this data sheet. pllv ? l9 a # pll voltage supply jtag emulation tms v14 i ipu jtag test-port mode select tdo w16 o/z ipu jtag test-port data out tdi aa17 i ipu jtag test-port data in tck y15 i ipu jtag test-port clock trst y14 i ipd jtag test-port reset. for ieee 1149.1 jtag compatibility, see the ieee 1149.1 jtag compatibility statement section of this data sheet. emu11 v15 i/o/z ipu emulation pin 11. reserved for future use, leave unconnected. emu10 y16 i/o/z ipu emulation pin 10. reserved for future use, leave unconnected. emu9 t14 i/o/z ipu emulation pin 9. reserved for future use, leave unconnected. emu8 u14 i/o/z ipu emulation pin 8. reserved for future use, leave unconnected. emu7 ab18 i/o/z ipu emulation pin 7. reserved for future use, leave unconnected. emu6 aa16 i/o/z ipu emulation pin 6. reserved for future use, leave unconnected. emu5 w15 i/o/z ipu emulation pin 5. reserved for future use, leave unconnected. emu4 ab17 i/o/z ipu emulation pin 4. reserved for future use, leave unconnected. emu3 w14 i/o/z ipu emulation pin 3. reserved for future use, leave unconnected. emu2 aa15 i/o/z ipu emulation pin 2. reserved for future use, leave unconnected. emu1 emu0 t13 v13 i/o/z ipu emulation [1:0] pins ? select the device functional mode of operation emu[1:0] operation 00 boundary scan/normal mode (see note) 01 reserved 10 reserved 11 emulation/normal mode [default] (see the ieee 1149.1 jtag compatibility statement section of this data sheet) normal mode refers to the dsps normal operational mode, when the dsp is free running. the dsp can be placed in normal operational mode when the emu[1:0] pins are configured for either boundary scan or emulation. note: when the emu[1:0] pins are configured for boundary scan mode, the internal pulldown (ipd) on the trst signal must not be opposed in order to operate in normal mode. for the boundary scan mode pulldown emu[1:0] pins with a dedicated 1-k ? resister. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. ? pllv is not part of external voltage supply. see the clock pll section for information on how to connect this pin. # a = analog signal (pll filter)
sgus050a ? january 2004 ? revised march 2004 42 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description resets, interrupts, and general-purpose input/outputs reset ab5 i device reset nmi e6 i ipd nonmaskable interrupt, edge-driven (rising edge) gp7/ext_int7 y6 general-purpose input/output (gpio) pins ( i/o/z ) or external interrupts ( input only ). the default after reset setting is gpio enabled as input-only. gp6/ext_int6 v8 i/o/z ipu general-purpose input/output (gpio) pins ( i/o/z ) or external interrupts ( input only ). the default after reset setting is gpio enabled as input-only. when these pins function as external interrupts [by selecting the corresponding interrupt gp5/ext_int5 aa5 i/o/z ipu ? when these pins function as external interrupts [by selecting the corresponding interrupt enable register bit (ier.[7:4])], they are edge-driven and the polarity can be gp4/ext_int4 u9 enable register bit (ier.[7:4])], they are edge-driven and the polarity can be independently selected via the external interrupt polarity register bits (extpol.[3:0]) . gp15/prst j8 general-purpose input/output (gpio) 15 pin ( i/o/z ) or pci reset ( i ). no function at default. gp14/pclk g5 gpio 14 pin ( i/o/z ) or pci clock ( i ). no function at default. gp13/pinta g4 gpio 13 pin ( i/o/z ) or pci interrupt a ( o/z ). no function at default. gp12/pgnt j7 gpio 12 pin ( i/o/z ) or pci bus grant ( i ). no function at default. gp11/preq h6 gpio 11 pin ( i/o/z ) or pci bus request ( o/z ). no function at default. gp10/pcbe3 l7 i/o/z gpio 10 pin ( i/o/z ) or pci command/byte enable 3 ( i/o/z ). no function at default. gp9/pidsel k6 i/o/z gpio 9 pin ( i/o/z ) or pci initialization device select ( i ). no function at default. gp3 aa6 ipd gpio 3 pin ( i/o/z ). the default after reset setting is gpio 3 enabled as input-only. gp0 w8 ipd gpio 0 pin. the general-purpose i/o 0 pin (gpio 0) ( i/o/z ) can be programmed as gpio 0 ( input only ) [default] or as g pio 0 ( output only ) pin or output as a general-purpose interrupt (gp0int) signal ( output only ). clks2/gp8 ? w7 i/o/z ipd mcbsp2 external clock source (clks2) [ input only ] [default] or this pin can be pro- grammed as a gpio 8 pin ( i/o/z ). clkout6/gp2 ? t10 i/o/z ipd clock output at 1/6 of the device speed ( o/z ) [default] or this pin can be programmed as a gpio 2 pin ( i/o/z ). clkout4/gp1 ? y7 i/o/z ipd clock output at 1/4 of the device speed ( o/z ) [default] or this pin can be programmed as a gpio 1 pin ( i/o/z ). host-port interface (hpi) [c64x] or peripheral component interconnect (pci) [c6415 or c6416 devices only] pci_en t8 i ipd pci enable pin. this pin controls the selection (enable/disable) of the hpi and gp[15:9], or pci peripherals (for the c6415 and c6416 devices). this pin works in conjunction with the mcbsp2_en pin to enable/disable other peripherals (for more details, see the device con- figurations section of this data sheet). the c6414 device does not support the pci peripheral; for proper device operation, do not oppose the internal pulldown (ipd) on this pin. hint /pframe p4 i/o/z host interrupt from dsp to host ( o ) [default] or pci frame ( i/o/z ) hcntl1/ pdevsel n8 i/o/z host control ? selects between control, address, or data registers ( i ) [default] or pci device select ( i/o/z ). hcntl0/ pstop p5 i/o/z host control ? selects between control, address, or data registers ( i ) [default] or pci stop ( i/o/z ) hhwil/ptrdy n5 i/o/z host half-word select ? first or second half-word (not necessarily high or low order) [for hpi16 bus width selection only] ( i ) [default] or pci target ready ( i/o/z ) hr/w /pcbe2 n6 i/o/z host read or write select ( i ) [default] or pci command/byte enable 2 ( i/o/z ) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. ? for the c6414 device, only these pins are multiplexed pins.
sgus050a ? january 2004 ? revised march 2004 43 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description host-port interface (hpi) [c64x] or peripheral component interconnect (pci) [c6415 or c6416 devices only] (continued) has /ppar n7 i/o/z host address strobe ( i ) [default] or pci parity ( i/o/z ) hcs /pperr n9 i/o/z host chip select ( i ) [default] or pci parity error ( i/o/z ) hds1 /pserr r5 i/o/z host data strobe 1 ( i ) [default] or pci system error ( i/o/z ) hds2 /pcbe1 p6 i/o/z host data strobe 2 ( i ) [default] or pci command/byte enable 1 ( i/o/z ) hrdy /pirdy n4 i/o/z host ready from dsp to host ( o ) [default] or pci initiator ready ( i/o/z ). hd31/ad31 j4 hd30/ad30 k7 hd29/ad29 j5 hd28/ad28 k4 hd27/ad27 k5 hd26/ad26 l6 hd25/ad25 l8 hd24/ad24 j6 hd23/ad23 l5 hd22/ad22 m5 host-port data ( i/o/z ) [default] (c64x) or pci data-address bus ( i/o/z ) [c6415 and c6416] hd21/ad21 m6 as hpi data bus (pci_en pin = 0) hd20/ad20 m8 as hpi data bus (pci_en pin = 0) ? used for transfer of data, address, and control hd19/ad19 l4 ? used for transfer of data, address, and control ? host-port bus width user-configurable at device reset via a 10-k ? resistor pullup/pulldown resistor on the hd5 pin: hd18/ad18 m4 resistor on the hd5 pin: hd17/ad17 m9 hd5 pin = 0: hpi operates as an hpi16. (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins are hd16/ad16 m7 i/o/z hd5 pin = 0: hpi operates as an hpi16. (hpi bus is 16 bits wide. hd[15:0] pins are used and the remaining hd[31:16] pins are reserved pins in the high-impedance state.) hd15/ad15 p8 i/o/z reserved pins in the high-impedance state.) hd14/ad14 r6 hd5 pin = 1: hpi operates as an hpi32. (hpi bus is 32 bits wide. all hd[31:0] pins are used for host-port operations.) hd13/ad13 r4 hd5 pin = 1: hpi operates as an hpi32. (hpi bus is 32 bits wide. all hd[31:0] pins are used for host-port operations.) hd12/ad12 p7 as pci data-address bus (pci_en pin = 1) [c6415 and c6416 devices only] hd11/ad11 r7 as pci data-address bus (pci_en pin = 1) [c6415 and c6416 devices only] ? used for transfer of data and address hd10/ad10 t5 used for transfer of data and address the c6414 device does not support the pci peripheral; therefore, the hpi peripheral pins are hd9/ad9 t4 the c6414 device does not support the pci peripheral; therefore, the hpi peripheral pins are standalone peripheral functions, not muxed. hd8/ad8 p9 standalone peripheral functions, not muxed. hd7/ad7 t6 hd6/ad6 r8 hd5/ad5 u4 hd4/ad4 u5 hd3/ad3 t7 hd2/ad2 u6 hd1/ad1 v4 hd0/ad0 v5 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device.
sgus050a ? january 2004 ? revised march 2004 44 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description host-port interface (hpi) [c64x] or peripheral component interconnect (pci) [c6415 or c6416 devices only] (continued) pcbe0 y3 i/o/z pci command/byte enable 0 ( i/o/z ). when pci is disabled (pci_en = 0), this pin is tied-off. for the c6414 device this pin is ?reserved (leave unconnected, do not connect to power or ground).? xsp_cs aa3 o ipd pci serial interface chip select ( o ). when pci is disabled (pci_en = 0), this pin is tied-off. for the c6414 device this pin is ?reserved (leave unconnected, do not connect to power or ground).? clkx2/ xsp_clk w5 i/o/z ipd mcbsp2 transmit clock ( i/o/z ) [default] or pci serial interface clock ( o ). dr2/xsp_di y4 i ipu mcbsp2 receive data ( i ) [default] or pci serial interface data in ( i ). in pci mode, this pin is connected to the output data pin of the serial prom. dx2/xsp_do r9 o/z ipu mcbsp2 transmit data ( o/z ) [default] or pci serial interface data out ( o ). in pci mode, this pin is connected to the input data pin of the serial prom. gp15/prst j8 general-purpose input/output (gpio) 15 pin ( i/o/z ) or pci reset ( i ). no function at default. gp14/pclk g5 gpio 14 pin ( i/o/z ) or pci clock ( i ). no function at default. gp13/pinta g4 gpio 13 pin ( i/o/z ) or pci interrupt a ( o/z ). no function at default. gp12/pgnt j7 i/o/z gpio 12 pin ( i/o/z ) or pci bus grant ( i ). no function at default. gp11/preq h6 i/o/z gpio 11 pin ( i/o/z ) or pci bus request ( o/z ). no function at default. gp10/pcbe3 l7 gpio 10 pin ( i/o/z ) or pci command/byte enable 3 ( i/o/z ). no function at default. gp9/pidsel k6 gpio 9 pin ( i/o/z ) or pci initialization device select ( i ). no function at default. emifa (64-bit) ? control signals common to all types of memory || ace3 k20 o/z ipu emifa memory space enables ace2 l17 o/z ipu emifa memory space enables ? enabled by bits 28 through 31 of the word address ace1 j21 o/z ipu ? enabled by bits 28 through 31 of the word address ? only one pin is asserted during any external data access ace0 k19 o/z ipu ? only one pin is asserted during any external data access abe7 p19 o/z ipu abe6 u22 o/z ipu abe5 t22 o/z ipu emifa byte-enable control decoded from the low-order address bits. the number of address bits or byte enables abe4 r21 o/z ipu emifa byte-enable control ? decoded from the low-order address bits. the number of address bits or byte enables used depends on the width of external memory. abe3 m17 o/z ipu used depends on the width of external memory. ? byte-write enables for most types of memory abe2 m18 o/z ipu ? byte-write enables for most types of memory ? can be directly connected to sdram read and write mask signal (sdqm) abe1 h22 o/z ipu can be directly connected to sdram read and write mask signal (sdqm) abe0 l19 o/z ipu apdt l20 o/z ipu emifa peripheral data transfer, allows direct transfer between external peripherals ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 45 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifa (64-bit) ? bus arbitration || aholda m19 o ipu emifa hold-request-acknowledge to the host ahold u21 i ipu emifa hold request from the host abusreq p21 o ipu emifa bus request output emifa (64-bit) ? asynchronous/synchronous memory control || aeclkin j19 i ipd emifa external input clock. the emifa input clock (aeclkin, cpu/4 clock, or cpu/6 clock) is selected at reset via the pullup/pulldown resistors on the bea[17:16] pins. aeclkin is the default for the emifa input clock. aeclkout2 k18 o/z ipd emifa output clock 2. programmable to be emifa input clock (aeclkin, cpu/4 clock, or cpu/6 clock) frequency divided-by-1, -2, or -4. aeclkout1 h21 o/z ipd emifa output clock 1 [at emifa input clock (aeclkin, cpu/4 clock, or cpu/6 clock) frequency]. aare / asdcas / asads /asre l16 o/z ipu emifa asynchronous memory read-enable/sdram column-address strobe/programmable synchronous interface-address strobe or read-enable ? for programmable synchronous interface, the renen field in the ce space secondary control register (cexsec) selects between asads and asre : if renen = 0, then the asads /asre signal functions as the asads signal. if renen = 1, then the asads /asre signal functions as the asre signal. aaoe / asdras / asoe j20 o/z ipu emifa asynchronous memory output-enable/sdram row-address strobe/programmable synchronous interface output-enable aawe / asdwe / aswe g22 o/z ipu emifa asynchronous memory write-enable/sdram write-enable/programmable synchro- nous interface write-enable asdcke k21 o/z ipu emifa sdram clock-enable (used for self-refresh mode). [emifa module only.] ? if sdram is not in system, asdcke can be used as a general-purpose output. asoe3 n16 o/z ipu emifa synchronous memory output-enable for ace3 (for glueless fifo interface) aardy l18 i ipu asynchronous memory ready input emifa (64-bit) ? address || aea22 r20 aea21 p16 aea20 t20 aea19 r18 aea18 v22 aea17 r19 o/z ipd emifa external address (doubleword address) aea16 t21 o/z ipd emifa external address (doubleword address) aea15 p17 aea14 n18 aea13 p18 aea12 p20 aea11 n17 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 46 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifa (64-bit) ? address || (continued) aea10 n20 aea9 n21 aea8 n19 aea7 m21 o/z ipd emifa external address (doubleword address) aea6 m20 o/z ipd emifa external address (doubleword address) aea5 l21 aea4 m16 aea3 j22 emifa (64-bit) ? data || aed63 ab21 aed62 w18 aed61 y19 aed60 v17 aed59 aa20 aed58 aa19 aed57 y18 aed56 t15 aed55 u16 aed54 ab20 aed53 aa18 aed52 v16 aed51 w17 aed50 y17 i/o/z ipu emifa external data aed49 u15 i/o/z ipu emifa external data aed48 ab19 aed47 t19 aed46 u20 aed45 r17 aed44 y22 aed43 v21 aed42 t18 aed41 u19 aed40 w21 aed39 v20 aed38 r16 aed37 t17 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 47 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifa (64-bit) ? data || (continued) aed36 u18 aed35 y21 aed34 v19 aed33 w20 aed32 aa22 aed31 d22 aed30 g19 aed29 f20 aed28 h18 aed27 e21 aed26 f21 aed25 g20 aed24 k16 aed23 j17 aed22 e22 aed21 g21 aed20 j18 aed19 h19 aed18 h20 i/o/z ipu emifa external data aed17 k17 i/o/z ipu emifa external data aed16 f22 aed15 f16 aed14 e17 aed13 h15 aed12 c20 aed11 d18 aed10 g16 aed9 f17 aed8 d19 aed7 e18 aed6 j15 aed5 h16 aed4 g17 aed3 d20 aed2 f18 aed1 e19 aed0 c21 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 48 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifb (16-bit) ? control signals common to all types of memory || bce3 d11 o/z ipu emifb memory space enables bce2 c9 o/z ipu emifb memory space enables ? enabled by bits 26 through 31 of the word address bce1 h12 o/z ipu ? enabled by bits 26 through 31 of the word address ? only one pin is asserted during any external data access bce0 g12 o/z ipu ? only one pin is asserted during any external data access bbe1 d12 o/z ipu emifb byte-enable control ? decoded from the low-order address bits. the number of address bits or byte enables used depends on the width of external memory. bbe0 e12 o/z ipu used depends on the width of external memory. ? byte-write enables for most types of memory ? can be directly connected to sdram read and write mask signal (sdqm) bpdt e11 o/z ipu emifb peripheral data transfer, allows direct transfer between external peripherals emifb (16-bit) ? bus arbitration || bholda f12 o ipu emifb hold-request-acknowledge to the host bhold c19 i ipu emifb hold request from the host bbusreq d14 o ipu emifb bus request output emifb (16-bit) ? asynchronous/synchronous memory control || beclkin e10 i ipd emifb external input clock. the emifb input clock (beclkin, cpu/4 clock, or cpu/6 clock) is selected at reset via the pullup/pulldown resistors on the bea[15:14] pins. beclkin is the default for the emifb input clock. beclkout2 c8 o/z ipd emifb output clock 2. programmable to be emifb input clock (beclkin, cpu/4 clock, or cpu/6 clock) frequency divided by 1, 2, or 4. beclkout1 j12 o/z ipd emifb output clock 1 [at emifb input clock (beclkin, cpu/4 clock, or cpu/6 clock) frequency]. bare / bsdcas / bsads /bsre c7 o/z ipu emifb asynchronous memory read-enable/sdram column-address strobe/programmable synchronous interface-address strobe or read-enable ? for programmable synchronous interface, the renen field in the ce space secondary control register (cexsec) selects between bsads and bsre : if renen = 0, then the bsads /bsre signal functions as the bsads signal. if renen = 1, then the bsads /bsre signal functions as the bsre signal. baoe / bsdras / bsoe d10 o/z ipu emifb asynchronous memory output-enable/sdram row-address strobe/programmable synchronous interface output-enable bawe /bsdwe / bswe f11 o/z ipu emifb asynchronous memory write-enable/sdram write-enable/programmable synchro- nous interface write-enable bsoe3 j13 o/z ipu emifb synchronous memory output enable for bce3 (for glueless fifo interface) bardy g11 i ipu emifb asynchronous memory ready input ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 49 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifb (16-bit) ? address || bea20 e15 ipu emifb external address (half-word address) ( o/z ) ? also controls initialization of dsp modes at reset ( i ) via pullup/pulldown resistors ? device endian mode bea19 d17 ipu also controls initialization of dsp modes at reset ( i ) via pullup/pulldown resistors ? device endian mode bea20: 0 ? big endian 1 ? little endian (default mode) bea18 j14 1 ? little endian (default mode) ? boot mode bea[19:18]: 00 ? no boot 01 ? hpi boot bea17 e16 bea[19:18]: 00 ? no boot 01 ? hpi boot 10 ? emifb 8-bit rom boot with default timings (default mode) 11 ? reserved bea16 g15 11 ? reserved ? emif clock select bea15 c18 ? emif clock select bea[17:16]: clock mode select for emifa (aeclkin_sel[1:0]) 00 ? aeclkin (default mode) 01 ? cpu/4 clock rate bea14 f15 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate 11 ? reserved bea13 d16 11 ? reserved bea[15:14]: clock mode select for emifb (beclkin_sel[1:0]) 00 ? beclkin (default mode) bea12 h14 bea[15:14]: clock mode select for emifb (beclkin_sel[1:0]) 00 ? beclkin (default mode) 01 ? cpu/4 clock rate 10 ? cpu/6 clock rate bea11 f14 10 ? cpu/6 clock rate 11 ? reserved bea10 c17 i/o/z ipd ? pci eeprom auto-initialization (eeai) [c6415 and c6416 devices only] bea13: pci auto-initialization via external eeprom if the pci peripheral is disabled (pci_en pin = 0), this pin must not be pulled up. bea9 g13 i/o/z ipd if the pci peripheral is disabled (pci_en pin = 0), this pin must not be pulled up. 0 ? pci auto-initialization through eeprom is disabled (default) . 1 ? pci auto-initialization through eeprom is enabled. bea8 g14 1 ? pci auto-initialization through eeprom is enabled. ? utopia enable (utopia_en) [c6415 and c6416 devices only] bea11: utopia peripheral enable (functional) bea7 e14 ? utopia enable (utopia_en) [c6415 and c6416 devices only] bea11: utopia peripheral enable (functional) 0 ? utopia disabled (mcbsp1 enabled) [default] 1 ? utopia enabled (mcbsp1 disabled) bea6 h13 1 ? utopia enabled (mcbsp1 disabled) the c6414 device does not support the pci and utopia peripherals; for proper device do not bea5 c16 the c6414 device does not support the pci and utopia peripherals; for proper device operation, do not oppose the internal pulldowns (ipds) on the bea13 and bea11 pins. also for proper c6414 device operation, do not oppose the ipds on the bea7, bea8, bea4 d15 also for proper c6414 device operation, do not oppose the ipds on the bea7, bea8, and bea9 pins. bea3 e13 for proper c6415 device operation, the bea7 pin must be externally pulled up with a 1-k ? resistor. bea2 d13 1-k resistor. for proper c6416 device operation, the bea8 and bea9 pins must be externally pulled up with a 1-k ? resistor. bea1 f13 up with a 1-k ? resistor. for more details, see the device configurations section of this data sheet. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 50 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description emifb (16-bit) ? data || bed15 f8 bed14 j10 bed13 d7 bed12 c5 bed11 h10 bed10 g9 bed9 c6 bed8 e8 i/o/z ipu emifb external data bed7 e9 i/o/z ipu emifb external data bed6 f9 bed5 g10 bed4 j11 bed3 d9 bed2 d8 bed1 h11 bed0 f10 multichannel buffered serial port 2 (mcbsp2) mcbsp2_en ab4 i ipd mcbsp2 enable pin. this pin works in conjunction with the pci_en pin to enable/disable other peripherals (for more details, see the device configurations section of this data sheet). clks2/gp8 w7 i/o/z ipd mcbsp2 external clock source (clks2) [ input only ] [default] or this pin can also be programmed as a gpio 8 pin ( i/o/z ). clkr2 w4 i/o/z ipd mcbsp2 receive clock. when mcbsp2 is disabled (pci_en = 1 and mcbsp2_en pin = 0), this pin is tied-off. clkx2/ xsp_clk w5 i/o/z ipd mcbsp2 transmit clock ( i/o/z ) [default] or pci serial interface clock ( o ). dr2/xsp_di y4 i ipu mcbsp2 receive data ( i ) [default] or pci serial interface data in ( i ). in pci mode, this pin is connected to the output data pin of the serial prom. dx2/xsp_do r9 o/z ipu mcbsp2 transmit data ( o/z ) [default] or pci serial interface data out ( o ). in pci mode, this pin is connected to the input data pin of the serial prom. fsr2 v6 i/o/z ipd mcbsp2 receive frame sync. when mcbsp2 is disabled (pci_en = 1 and mcbsp2_en pin = 0), this pin is tied-off. fsx2 u7 i/o/z ipd mcbsp2 transmit frame sync. when mcbsp2 is disabled (pci_en = 1 and mcbsp2_en pin = 0), this pin is tied-off. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins except clks2/gp8 are standalone peripheral functions for this device. || these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). the prefix ?a? in front of a signal name indicates it is an emifa sign al whereas a prefix ?b? in front of a signal name indicates it is an emifb signal. throughout the rest of this document, in generi c emif areas of discussion, the prefix ?a? or ?b? may be omitted from the signal name. to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
sgus050a ? january 2004 ? revised march 2004 51 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description multichannel buffered serial port 1 (mcbsp1) clks1/ uraddr3 y8 i mcbsp1 external clock source (as opposed to internal) ( i ) [default] or utopia receive address 3 pin ( i ) clkr1/ uraddr2 ab7 i/o/z mcbsp1 receive clock ( i/o/z ) [default] or utopia receive address 2 pin ( i ) clkx1/ uraddr4 t12 i/o/z mcbsp1 transmit clock ( i/o/z ) [default] or utopia receive address 4 pin ( i ) dr1/ uxaddr1 v11 i mcbsp1 receive data ( i ) [default] or utopia transmit address 1 pin ( i ) dx1/ uxaddr4 y10 i/o/z mcbsp1 transmit data ( o/z ) [default] or utopia transmit address 4 pin ( i ) fsr1/ uxaddr2 aa8 i/o/z mcbsp1 receive frame sync ( i/o/z ) [default] or utopia transmit address 2 pin ( i ) fsx1/ uxaddr3 aa11 i/o/z mcbsp1 transmit frame sync ( i/o/z ) [default] or utopia transmit address 3 pin ( i ) multichannel buffered serial port 0 (mcbsp0) clks0 f4 i ipd mcbsp0 external clock source (as opposed to internal) clkr0 f5 i/o/z ipd mcbsp0 receive clock clkx0 k9 i/o/z ipd mcbsp0 transmit clock dr0 g6 i ipu mcbsp0 receive data dx0 e4 o/z ipu mcbsp0 transmit data fsr0 d3 i/o/z ipd mcbsp0 receive frame sync fsx0 h7 i/o/z ipd mcbsp0 transmit frame sync timer 2 tout2 f7 o/z ipd timer 2 or general-purpose output tinp2 d5 i ipd timer 2 or general-purpose input timer 1 tout1 g8 o/z ipd timer 1 or general-purpose output tinp1 d6 i ipd timer 1 or general-purpose input timer 0 tout0 h9 o/z ipd timer 0 or general-purpose output tinp0 e7 i ipd timer 0 or general-purpose input ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device.
sgus050a ? january 2004 ? revised march 2004 52 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description universal test and operations phy interface for asynchronous transfer mode (atm) [utopia slave] [c6415 and c6416 devices only] utopia slave (atm controller) ? transmit interface uxclk ab8 i source clock for utopia transmit driven by master atm controller. when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. uxclav aa13 o/z transmit cell available status output signal from utopia slave. 0 indicates a complete cell is not available for transmit 1 indicates a complete cell is available for transmit when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. uxenb u13 i ? utopia transmit interface enable input signal. asserted by the master atm controller to indi- cate that the utopia slave should put out on the transmit data bus the first byte of valid data and the uxsoc signal in the next clock cycle. when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. uxsoc y12 o/z transmit start-of-cell signal. this signal is output by the ut opia slave on the rising edge of the uxclk, indicating that the first valid byte of the cell is available on the 8-bit t ransmit data bus (uxdata[7:0]). when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. dx1/ uxaddr4 y10 i/o/z ? mcbsp1 [default] or utopia transmit address pins as utopia transmit address pins uxaddr[4:0] ( i ), utopia_en (bea11 pin) = 1: ? 5-bit slave transmit address input pins driven by the master atm controller to identify and select one of the slave devices (up to 31 possible) in the atm system. ? uxaddr0 pin is tied off when the utopia peripheral is disabled [utopia_en (bea11 pin) = 0] for the mcbsp1 pin functions (ut opia_en (bea11 pin) = 0 [default]), see the mul tichan- nel buffered serial port 1 (mcbsp1) section of this table. fsx1/ uxaddr3 aa11 i/o/z ? mcbsp1 [default] or utopia transmit address pins as utopia transmit address pins uxaddr[4:0] ( i ), utopia_en (bea11 pin) = 1: fsr1/ uxaddr2 aa8 i/o/z ? as utopia transmit address pins uxaddr[4:0] ( i ), utopia_en (bea11 pin) = 1: ? 5-bit slave transmit address input pins driven by the master atm controller to identify and select one of the slave devices (up to 31 possible) in the atm system. dr1/ uxaddr1 v11 i ? ? uxaddr0 pin is tied off when the utopia peripheral is disabled [utopia_en (bea11 pin) = 0] for the mcbsp1 pin functions (ut opia_en (bea11 pin) = 0 [default]), see the mul tichan- uxaddr0 y9 i ? for the mcbsp1 pin functions (ut opia_en (bea11 pin) = 0 [default]), see the mul tichan - nel buffered serial port 1 (mcbsp1) section of this table. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) for the c6415 and c6416 devices, these pins are multiplexed pins. for more details, see the device configurations section of th is data sheet. the c6414 device does not support the pci or ut opia peripherals; therefore, these muxed peripheral pins are standalone peripheral functions for this device. for the c6415 and c6416 devices, external pulldowns required: if utopia is selected (bea11 = 1) and these pins are connected to other devices, then a 10-k ? resistor must be used to externally pull down each of these pins. if these pins are ?no connects?, then only uxclk and urclk need to be pulled down and other pulldowns are not necessary. ? for the c6415 and c6416 devices, external pullups required: if utopia is selected (bea11 = 1) and these pins are connected to other devices, then a 10-k ? resistor must be used to externally pull up each of these pins. if these pins are ?no connects?, then the pullups are not necessary. the c6414 device does not support the utopia peripheral; therefore, these standalone utopia pins are reserved (leave unconnected, do not connect to power or ground) with the exception of uxclk and urclk which should be connected to a 10-k ? pulldown resistor (see the square [ ] footnote).
sgus050a ? january 2004 ? revised march 2004 53 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description utopia slave (atm controller) ? transmit interface (continued) uxdata7 w10 uxdata6 t11 uxdata5 w9 8-bit transmit data bus using the t ransmit data bus, the utopia slave (on the rising edge of the uxclk) transmits uxdata4 ab6 o/z 8-bit transmit data bus using the t ransmit data bus, the utopia slave (on the rising edge of the uxclk) transmit s the 8-bit atm cells to the master atm controller. uxdata3 v10 o/z the 8-bit atm cells to the master atm controller. when the ut opia peripheral is disabled (ut opia_en [bea11 pin] = 0), these pins are tied- uxdata2 u10 when the ut opia peripheral is disabled (ut opia_en [bea11 pin] = 0), these pins are tied- off. uxdata1 aa7 off. uxdata0 v9 utopia slave (atm controller) ? receive interface urclk u12 i source clock for utopia receive driven by master atm controller. when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. urclav aa14 o/z receive cell available status output signal from utopia slave. 0 indicates no space is available to receive a cell from master atm controller 1 indicates space is available to receive a cell from master atm controller when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. urenb ab16 i ? utopia receive interface enable input signal. asserted by the master atm controller to indi- cate to the ut opia slave to sample the receive data bus (urdata[7:0]) and ursoc signal in the next clock cycle or thereafter. when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. ursoc w13 i receive start-of-cell signal. this signal is output by the master atm controller to indicate to the utopia slave that the first valid byte of the cell is available to sample on the 8-bit receive data bus (urdata[7:0]). when the utopia peripheral is disabled (utopia_en [bea11 pin] = 0), this pin is tied-off. clkx1/ uraddr4 t12 i/o/z ? mcbsp1 [default] or utopia receive address pins as utopia receive address pins uraddr[4:0] ( i ), utopia_en (bea11 pin) = 1: clks1/ uraddr3 y8 i ? as utopia receive address pins uraddr[4:0] ( i ), utopia_en (bea11 pin) = 1: ? 5-bit slave receive address input pins driven by the master atm controller to identify and select one of the slave devices (up to 31 possible) in the atm system. clkr1/ uraddr2 ab7 i/o/z ? select one of the slave devices (up to 31 possible) in the atm system. ? uraddr1 and uraddr0 pins are tied off when the utopia peripheral is disabled [utopia_en (bea11 pin) = 0] uraddr1 u11 i ? [utopia_en (bea11 pin) = 0] for the mcbsp1 pin functions (ut opia_en (bea11 pin) = 0 [default]), see the mul tichan- uraddr0 aa9 i ? for the mcbsp1 pin functions (ut opia_en (bea11 pin) = 0 [default]), see the mul tichan- nel buffered serial port 1 (mcbsp1) section of this table. ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) these pins are multiplexed pins. for more details, see the device configurations section of this data sheet. external pulldowns required: if utopia is selected (bea11 = 1) and these pins are connected to other devices, then a 10-k ? resistor must be used to externally pull down each of these pins. if these pins are ?no connects?, then only uxclk and urclk need to be pulled down and other pulldowns are not necessary. ? external pullups required: if utopia is selected (bea11 = 1) and these pins are connected to other devices, then a 10-k ? resistor must be used to externally pull up each of these pins. if these pins are ?no connects?, then the pullups are not necessary. the c6414 device does not support the utopia peripheral; therefore, these standalone utopia pins are reserved (leave unconnected, do not connect to power or ground) with the exception of uxclk and urclk which should be connected to a 10-k ? pulldown resistor (see the square [ ] footnote).
sgus050a ? january 2004 ? revised march 2004 54 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? ipd/ ? description name no. type ? ipd/ ipu ? description utopia slave (atm controller) ? receive interface (continued) urdata7 aa10 urdata6 v12 urdata5 w12 8-bit receive data bus. using the receive data bus, the utopia slave (on the rising edge of the urclk) can receive urdata4 w11 i y11 i the 8-bit atm cell data from the master atm controller. when the ut opia peripheral is disabled (ut opia_en [bea11 pin] = 0), these pins are tied- urdata2 ab9 when the ut opia peripheral is disabled (ut opia_en [bea11 pin] = 0), these pins are tied- off. urdata1 y13 off. urdata0 aa12 reserved for test c4 h5 rsv h3 reserved (leave unconnected, do not connect to power or ground) rsv n3 reserved (leave unconnected, do not connect to power or ground) p3 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. (these ipd/ipu signal pins feature a 30-k ? ipd or ipu resistor. to pull up a signal to the opposite supply rail, a 1-k ? resistor should be used.) external pulldowns required: if utopia is selected (bea11 = 1) and these pins are connected to other devices, then a 10-k ? resistor must be used to externally pull down each of these pins. if these pins are ?no connects?, then only uxclk and urclk need to be pulled down and other pulldowns are not necessary. the c6414 device does not support the utopia peripheral; therefore, these standalone utopia pins are reserved (leave unconnected, do not connect to power or ground) with the exception of uxclk and urclk which should be connected to a 10-k ? pulldown resistor (see the square [ ] footnote).
sgus050a ? january 2004 ? revised march 2004 55 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description supply voltage pins aa23 ab10 ab11 ab14 ab15 ab2 ab23 ac10 ac12 ac14 ac16 ac19 ac21 ac22 ac3 ac4 ac6 ac8 b11 b13 dv dd b15 s 3.3-v supply voltage dv dd b17 s 3.3-v supply voltage (see the power-supply decoupling section of this data sheet) b19 (see the power-supply decoupling section of this data sheet) b21 b22 b3 b4 b6 b9 c10 c11 c14 c15 c23 d2 d23 f2 f23 f3 g3 h2 j23 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 56 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description supply voltage pins (continued) j3 k2 k22 k3 l22 l23 m2 n23 p2 p22 3.3-v supply voltage dv dd r22 s 3.3-v supply voltage (see the power-supply decoupling section of this data sheet) dv dd r23 s (see the power-supply decoupling section of this data sheet) t2 t3 u23 u3 v2 v3 w23 w3 y2 a10 a12 a14 a16 a18 a20 a22 a4 a6 a8 1.4 v supply voltage cv dd aa1 s 1.4 v supply voltage (see the power-supply decoupling section of this data sheet) cv dd ab12 s (see the power-supply decoupling section of this data sheet) ab13 ab24 ac18 ac20 ac5 ad11 ad13 ad15 ad17 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 57 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description supply voltage pins (continued) ad19 ad21 ad23 ad3 ad5 ad7 ad9 b20 b24 b5 b7 c1 c12 c13 c2 d24 e1 e23 f24 1.4 v supply voltage cv dd g1 s 1.4 v supply voltage (see the power-supply decoupling section of this data sheet) cv dd g23 s (see the power-supply decoupling section of this data sheet) h24 j1 k10 k12 k14 k24 l1 l11 l13 l15 l3 m10 m12 m14 m22 m24 m3 n1 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 58 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description supply voltage pins (continued n11 n13 n15 n22 p10 p12 p14 p24 r1 1.4 v supply voltage cv dd r11 s 1.4 v supply voltage (see the power-supply decoupling section of this data sheet) cv dd r13 s (see the power-supply decoupling section of this data sheet) r15 r3 t24 u1 v24 w1 y23 y24 ground pins a11 a13 a15 a17 a19 a21 a23 a3 a5 a7 v ss a9 gnd ground pins v ss aa2 gnd ground pins aa21 aa24 aa4 ab1 ab22 ab3 ac1 ac11 ac13 ac15 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 59 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description ground pins ac17 ac2 ac23 ac24 ac7 ac9 ad10 ad12 ad14 ad16 ad18 ad2 ad20 ad22 ad4 ad6 ad8 b10 b12 v ss b14 gnd ground pins v ss b16 gnd ground pins b18 b2 b23 b8 c22 c24 c3 d1 d21 d4 e2 e20 e24 e5 f1 f19 f6 g18 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 60 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description ground pins (continued) g2 g24 g7 h1 h17 h23 h8 j16 j2 j24 j9 k1 k11 k13 k15 k23 l10 l12 l14 v ss l2 gnd ground pins v ss l24 gnd ground pins m1 m11 m13 m15 m23 n10 n12 n14 n2 n24 p1 p11 p13 p15 p23 r10 r12 r14 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 61 post office box 1443 ? houston, texas 77251?1443 terminal functions (continued) signal type ? description name no. type ? description ground pins (continued) r2 r24 t1 t16 t23 t9 u17 u2 u24 u8 v ss v1 gnd ground pins v ss v18 gnd ground pins v23 v7 w19 w2 w24 w6 y1 y20 y5 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sgus050a ? january 2004 ? revised march 2004 62 post office box 1443 ? houston, texas 77251?1443 development support ti offers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of c6000 ? dsp-based applications: software development tools: code composer studio ? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios ? ), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 ? dsp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320c6000 ? dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. code composer studio, dsp/bios, and xds are trademarks of texas instruments.
sgus050a ? january 2004 ? revised march 2004 63 post office box 1443 ? houston, texas 77251?1443 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each military tms320 ? dsp family member has one of three prefixes: smx, tmp, or smj. texas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (smx / tmdx) through fully qualified production devices/tools (smj / tmds). device development evolutionary flow: smx preproduction device that is not necessarily representative of the final device?s electrical specifications tmp final silicon die that conforms to the device?s electrical specifications but has not completed quality and reliability verification smj fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed t exas instruments internal qualification testing. tmds fully qualified development-support product smx and tmp devices and tmdx development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. experimental devices (smx) may not be representative of a final product and texas instruments reserves the right to change or discontinue these products without notice. smj devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. predictions show that preproduction or prototype devices (smx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, gad), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -6e3 is 600-mhz cpu, 133-mhz emifa). figure 4 provides a legend for reading the complete device name for any smj320c64x ? dsp generation member. tms320 is a trademark of texas instruments.
sgus050a ? january 2004 ? revised march 2004 64 post office box 1443 ? houston, texas 77251?1443 device and development-support tool nomenclature (continued) table 30. smj320c6414/c6415/c6416 device part numbers (p/ns) and ordering information device orderable p/n device speed, emif speed, silicon revision cv dd (core voltage) dv dd (i/o voltage) operating case temperature range c6414 smj320c6414dgadw60 ? 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c sm320c6414dgadw60 ? 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c c6415 smj320c6415dgadw60 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c sm320c6415dgadw60 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c c6416 smj320c6416dgadw60 ? 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c sm320c6416dgadw60 ? 600 mhz/4800 mips, 133-mhz emifa, silicon rev. 1.1 1.4 v 3.3 v ?55 c to 115 c ? product preview
sgus050a ? january 2004 ? revised march 2004 65 post office box 1443 ? houston, texas 77251?1443 device and development-support tool nomenclature (continued) c64x dsp: 6411 6414d 6414c 6415d 6415c 6416d 6416c prefix device speed range smj 32 c 6415c gad 6e3 tmx = experimental device tmp = prototype device tms = qualified device smx= preproduction device, mil smj = mil-prf-38535, qml sm = commercial processing device family 3 or 32 or 320 = tms320 dsp family technology package type glz = 532-pin plastic bga gad = 570-pin ceramic micro pin pga c = cmos device ? ? see the recommended operating conditions section of this data sheet for more details. ? the extended temperature ?a version? devices may have different operating conditions than the commercial temperature devices. see the recommended operating conditions section of this data sheet for more details. bga = ball grid array. pga = pin grid array. ? for the actual device part numbers (p/ns) and ordering information, see table 30 of this data sheet. temperature range (default: 0 c to 90 c) ? ( ) blank = 0 c to 90 c, commercial temperature a = ?40 c to 105 c, extended temperature ? w = ?55 c to 115 c, mil temp 300 5e0 (500-mhz cpu, 100-mhz emif) 6e3 (600-mhz cpu, 133-mhz emifa) 7e3 (720-mhz cpu, 133-mhz emifa) 60 (600-mhz cpu, 133-mhz emifa) milita ry figure 4. smj320c64x ? dsp device nomenclature (including the c6414, c6415, and c6416 devices)
sgus050a ? january 2004 ? revised march 2004 66 post office box 1443 ? houston, texas 77251?1443 documentation support extensive documentation supports all tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user?s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the c6000 ? dsp devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? dsp cpu (core) architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 dsp peripherals overview reference guide (literature number spru190) provides an overview and briefly describes the functionality of the peripherals available on the c6000 ? dsp platform of devices. this document also includes a table listing the peripherals available on the c6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. the tms320c64x technical overview (literature number spru395) gives an introduction to the c64x ? digital signal processor, and discusses the application areas that are enhanced by the c64x ? dsp v elociti.2 ? vliw architecture. the tms320c6414, tms320c6415, and tms320c6416 digital signal processors silicon errata (literature number sprz011) describes the known exceptions to the functional specifications for the smj320c6414, smj320c6415, and smj320c6416 devices. the tms320c6414/15/16 power consumption summary application report (literature number spra811) discusses the power consumption for user applications with the smj320c6414, smj320c6415, and smj320c6416 dsp devices. the using ibis models for timing analysis application report (literature number spra839) describes how to properly use ibis models to attain accurate timing analysis for a given system. the tools support documentation is electronically available within the code composer studio ? integrated development environment (ide). for a complete listing of c6000 ? dsp latest documentation, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). see the worldwide web url for the how to begin development today with the tms320c6414, tms320c6415, and tms320c6416 dsps application report (literature number spra718), which describes in more details the compatibility and similarities/differences among the c6414, c6415, c6416, and c6211 devices.
sgus050a ? january 2004 ? revised march 2004 67 post office box 1443 ? houston, texas 77251?1443 clock pll most of the internal c64x ? dsp clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which multiplies the source clock frequency to generate the internal cpu clock, or bypasses the pll to become the internal cpu clock. to use the pll to generate the cpu clock, the external pll filter circuit must be properly designed. figure 5 shows the external pll circuitry for either x1 (pll bypass) or other pll multiply modes. to minimize the clock jitter, a single clean power supply should power both the c64x ? dsp device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see the input and output clocks electrical section. rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the dsp requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electrical section). table 31 lists some examples of compatible clkin external clock sources: table 31. compatible clkin external clock sources compatible parts for external clock sources (clkin) part number manufacturer jito-2 fox electronix oscillators sta series, st4100 series saronix corporation oscillators sg-636 epson america 342 corning frequency control pll ics525-02 integrated circuit systems
sgus050a ? january 2004 ? revised march 2004 68 post office box 1443 ? houston, texas 77251?1443 clock pll (continued) pllmult 1 0 pllclk clkmode0 clkmode1 clkin c2 c1 emi filter 3.3 v /2 /8 /4 /6 00 01 10 cpu clock peripheral bus timer internal clock clkout4, mcbsp internal clock clkout6 eclkin_sel (devcfg.[17,16] and devcfg.[15,14]) /2 /4 emif 00 01 10 ek2rate (gblctl.[19,18]) eclkout2 eclkout1 pll x6, x12 10 f 0.1 f eclkin (for the pll options, clkmode pins setup, and pll clock frequency ranges, see table 32.) internal to c64x pllv notes: a. place all pll external components (c1, c2, and the emi filter) as close to the c6000 ? dsp device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer tdk part number acf451832-333, -223, -153, -103. panasonic part number exccet103u. figure 5. external pll circuitry for either pll multiply modes or x1 (bypass) mode
sgus050a ? january 2004 ? revised march 2004 69 post office box 1443 ? houston, texas 77251?1443 clock pll (continued) table 32. smj320c64x pll multiply factor options, clock frequency ranges, and typical lock time ?? gad package ? micro pin pga clkmode1 clkmode0 clkmode (pll multiply factors) clkin range (mhz) cpu clock frequency range (mhz) clkout4 range (mhz) clkout6 range (mhz) typical lock time ( s) 0 0 bypass (x1) 30?75 30?75 7.5?18.8 5?12.5 n/a 0 1 x6 30?75 180?450 45?112.5 30?75 75 1 0 x12 30?60 360?720 90?180 60?120 75 1 1 reserved ? ? ? ? ? ? these clock frequency range values are applicable to a c64x?60 speed device.. ? use external pullup resistors on the clkmode pins (clkmode1 and clkmode0) to set the c64x device to one of the valid pll multip ly clock modes (x6 or x12). with internal pulldown resistors on the clkmode pins (clkmode1, clkmode0), the default clock mode is x1 (byp ass). under some operating conditions, the maximum pll lock time may vary by as much as 150% from the specified typical value. for ex ample, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
sgus050a ? january 2004 ? revised march 2004 70 post office box 1443 ? houston, texas 77251?1443 general-purpose input/output (gpio) to use the gp[15:0] software-configurable gpio pins, the gpxen bits in the gp enable (gpen) register and the gpxdir bits in the gp direction (gpdir) register must be properly configured. gpxen = 1 gp[x] pin is enabled gpxdir = 0 gp[x] pin is an input gpxdir = 1 gp[x] pin is an output where ?x? represents one of the 15 through 0 gpio pins figure 6 shows the gpio enable bits in the gpen register for the c6414/c6415/c6416 device. to use any of the gpx pins as general-purpose input/output functions, the corresponding gpxen bit must be set to ?1? (enabled). default values are device-specific, so refer to figure 6 for the c6414/15/16 default configuration. 31 24 23 16 reserved r-0 15 14 13 12 11 10 9 8 7 6543 210 gp15 en gp14 en gp13 en gp12 en gp11 en gp10 en gp9 en gp8 en gp7 en gp6 en gp5 en gp4 en gp3 en gp2 en gp1 en gp0 en r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 legend: r/w = readable/writable; - n = value after reset, -x = undefined value after reset figure 6. gpio enable register (gpen) [hex address: 01b0 0000] figure 7 shows the gpio direction bits in the gpdir register. this register determines if a given gpio pin is an input or an output providing the corresponding gpxen bit is enabled (set to ?1?) in the gpen register. by default, all the gpio pins are configured as input pins. 31 24 23 16 reserved r-0 15 14 13 12 11 10 98 7 6 5 43 2 10 gp15 dir gp14 dir gp13 dir gp12 dir gp11 dir gp10 dir gp9 dir gp8 dir gp7 dir gp6 dir gp5 dir gp4 dir gp3 dir gp2 dir gp1 dir gp0 dir r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = readable/writable; - n = value after reset, -x = undefined value after reset figure 7. gpio direction register (gpdir) [hex address: 01b0 0004] for more detailed information on general-purpose inputs/outputs (gpios), see the tms320c6000 dsp general-purpose input/output (gpio) reference guide (literature number spru584).
sgus050a ? january 2004 ? revised march 2004 71 post office box 1443 ? houston, texas 77251?1443 power-down mode logic figure 8 shows the power-down mode logic on the c6414/c6415/c6416. pwrd internal clock tree cpu ifr ier csr pd1 pd2 power- down logic clock pll clkin reset clkout6 pd3 internal peripherals clkout4 clock and dividers distribution ? external input clocks, with the exception of clkin, are not gated by the power-down mode logic. smj320c6414/15/16 figure 8. power-down mode logic ? triggering, wake-up, and effects the power-down modes and their wake-up methods are programmed by setting the pwrd field (bits 15?10) of the control status register (csr). the pwrd field of the csr is shown in figure 9 and described in t able 33. when writing to the csr, all bits of the pwrd field should be set at the same time. logic 0 should be used when writing to the reserved bit (bit 15) of the pwrd field. the csr is discussed in detail in the tms320c6000 cpu and instruction set reference guide (literature number spru189).
sgus050a ? january 2004 ? revised march 2004 72 post office box 1443 ? houston, texas 77251?1443 31 16 15 14 13 12 11 10 9 8 reserved enable or non-enabled interrupt wake enabled interrupt wake pd3 pd2 pd1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 7 0 legend: r/w?x = read/write reset value note: the shadowed bits are not part of the power-down logic discussion and therefore are not covered here. for information on t hese other bit fields in the csr register, see the tms320c6000 cpu and instruction set reference guide (literature number spru189). figure 9. pwrd field of the csr register power-down mode pd1 takes effect eight to nine clock cycles after the instruction that sets the pwrd bits in the csr. if pd1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where pd1 took effect. if pd1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where pd1 took effect. pd2 and pd3 modes can only be aborted by device reset. table 33 summarizes all the power-down modes. table 33. characteristics of the power-down modes prwd field (bits 15?10) power-down mode wake-up method effect on chip?s operation 000000 no power-down ? ? 001001 pd1 wake by an enabled interrupt cpu halted (except for the interrupt logic) power-down mode blocks the internal clock inputs at the 010001 pd1 wake by an enabled or non-enabled interrupt power-down mode blocks the internal clock inputs at the boundary of the cpu, preventing most of the cpu?s logic from switching. during pd1, edma transactions can proceed between peripherals and internal memory. 011010 pd2 ? wake by a device reset output clock from pll is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. all register and internal ram contents are preserved. all functional i/o ?freeze? in the last state when the pll clock is turned off. 011100 pd3 ? wake by a device reset input clock to the pll stops generating clocks. all register and internal ram contents are preserv ed. all functional i/o ?freeze? in the last state when the pll clock is turned off. following reset, the pll needs time to re-lock, just as it does following power-up. wake-up from pd3 takes longer than wake-up from pd2 because the pll needs to be re-locked, just as it does following power-up. all others reserved ? ? ? when entering pd2 and pd3, all functional i/o remains in the previous state. however, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. under these con ditions, peripherals will not operate according to specifications.
sgus050a ? january 2004 ? revised march 2004 73 post office box 1443 ? houston, texas 77251?1443 c64x power-down mode with an emulator if user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow the emulator access to the system. this condition prevails until the emulator is reset or the cable is removed from the header. if power measurements are to be performed when in a power-down mode, the emulator cable should be removed. when the dsp is in power-down mode pd2 or pd3, emulation logic will force any emulation execution command (such as step or run) to spin in idle. for this reason, pc writes (such as loading code) will fail. a dsp reset will be required to get the dsp out of pd2/pd3. power-supply sequencing ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time ( > 1 second) if the other supply is below the proper operating voltage. power-supply design considerations a dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and i/o power up. a schottky diode can also be used to tie the core rail to the i/o rail (see figure 10). dv dd cv dd v ss c6000 dsp schottky diode i/o supply core supply gnd figure 10. schottky diode diagram core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the c6000 ? platform of dsps, the pc board should include separate power planes for core, i/o, and ground, all bypassed with high-quality low-esl/esr capacitors. power-supply decoupling in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the i/o supply. these caps need to be close to the dsp, no more than 1.25 cm maximum distance to be effective. physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. as with the selection of any component, verification of capacitor availability over the product?s production lifetime should be considered.
sgus050a ? january 2004 ? revised march 2004 74 post office box 1443 ? houston, texas 77251?1443 ieee 1149.1 jtag compatibility statement the smj320c6414/15/16 dsp requires that both trst and reset be asserted upon power up to be properly initialized. while reset initializes the dsp core, trst initializes the dsp?s emulation logic. both resets are required for proper operation. while both trst and reset need to be asserted upon power up, only reset needs to be released for the dsp to boot properly. trst may be asserted indefinitely for normal operation, keeping the jtag port interface and dsp?s emulation logic in the reset state. trst only needs to be released when it is necessary to use a jtag controller to debug the dsp or exercise the dsp?s boundary scan functionality. for maximum reliability, the smj320c6414/15/16 dsp includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the dsp?s internal emulation logic will always be properly initialized. jtag controllers from t exas instruments actively drive trst high. however, some third-party jt ag controllers may not drive trst high but expect the use of a pullup resistor on trst . when using this type of jtag controller, assert trst to initialize the dsp after power up and externally drive trst high before attempting any emulation or boundary scan operations. following the release of reset , the low-to-high transition of trst must be ?seen? to latch the state of emu1 and emu0. the emu[1:0] pins configure the device for either boundary scan mode or emulation mode. for more detailed information, see the terminal functions section of this data sheet. emif device speed the rated emif speed, referring to both emifa and emifb, of these devices only applies to the sdram interface when in a system that meets the following requirements: ? 1 chip-enable (ce) space (maximum of 2 chips) of sdram connected to emif ? up to 1 ce space of buffers connected to emif ? emif trace lengths between 1 and 3 inches ? 166-mhz sdram for 133-mhz operation (applies only to emifa) ? 143-mhz sdram for 100-mhz operation other configurations may be possible, but timing analysis must be done to verify all ac timings are met. verification of ac timings is mandatory when using configurations other than those specified above. ti recommends utilizing i/o buffer information specification (ibis) to analyze all ac timings. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). to maintain signal integrity, serial termination resistors should be inserted into all emif output signal lines (see the terminal functions table for the emif output signals).
sgus050a ? january 2004 ? revised march 2004 75 post office box 1443 ? houston, texas 77251?1443 bootmode the c6414/15/16 device resets using the active-low signal reset . while reset is low, the device is held in reset and is initialized to the prescribed reset state. refer to reset timing for reset timing characteristics and states of device pins during reset. the release of reset starts the processor running with the prescribed device configuration and boot mode. the c6414/c6415/c6416 has three types of boot modes: host boot if host boot is selected, upon release of reset , the cpu is internally ?stalled? while the remainder of the device is released. during this period, an external host can initialize the cpu?s memory space as necessary through the host interface, including internal configuration registers, such as those that control the emif or other peripherals. for the c6414 device, the hpi peripheral is used for host boot. for the c6415/c6416 device, the hpi peripheral is used for host boot if pci_en = 0, and the pci peripheral is used for host boot if pci_en = 1. once the host is finished with all necessary initialization, it must set the dspint bit in the hpic register to complete the boot process. this transition causes the boot configuration logic to bring the cpu out of the ?stalled? state. the cpu then begins execution from address 0. the dspint condition is not latched by the cpu, because it occurs while the cpu is still internally ?stalled?. also, dspint brings the cpu out of the ?stalled? state only if the host boot process is selected. all memory may be written to and read by the host. this allows for the host to verify what it sends to the dsp if required. after the cpu is out of the ?stalled? state, the cpu needs to clear the dspint, otherwise, no more dspints can be received. emif boot (using default rom timings) upon the release of reset , the 1k-byte rom code located in the beginning of ce1 is copied to address 0 by the edma using the default rom timings, while the cpu is internally ?stalled?. the data should be stored in the endian format that the system is using. in this case, the emif automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. the transfer is automatically done by the edma as a single-frame block transfer from the rom to address 0. after completion of the block transfer, the cpu is released from the ?stalled? state and starts running from address 0. no boot with no boot, the cpu begins direct execution from the memory located at address 0. note: operation is undefined if invalid code is located at address 0.
sgus050a ? january 2004 ? revised march 2004 76 post office box 1443 ? houston, texas 77251?1443 absolute maximum ratings over operating case temperature range (unless otherwise noted) ? supply voltage ranges: cv dd (see note 1) ? 0.3 v to 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv dd (see note 1) ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage ranges: (except pci), v i ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v ip [c6415 and c6416 only] ?0.5 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . output voltage ranges: (except pci), v o ?0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v op [c6415 and c6416 only] ?0.5 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . operating case temperature ranges, t c : ?55 c to 115 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit cv dd supply voltage, core ? 1.36 1.4 1.44 v dv dd supply voltage, i/o 3.14 3.3 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage (except pci) 2 v v il low-level input voltage (except pci) 0.8 v v ip input voltage (pci) [c6415 and c6416 only] ?0.5 dv dd + 0.5 v v ihp high-level input voltage (pci) [c6415 and c6416 only] 0.5dv dd dv dd + 0.5 v v ilp low-level input voltage (pci) [c6415 and c6416 only] ?0.5 0.3dv dd v v os maximum voltage during overshoot/undershoot ?1.0 4.3 v t c operating case tem- perature w version ?55 115 c ? future variants of the c641x dsps may operate at voltages ranging from 0.9 v to 1.4 v to provide a range of system power/performance o ptions. ti highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 v, 1.25 v, 1. 3 v, 1.35 v, 1.4 v with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications . examples of such supplies include the pt4660, pt5500, pt5520, pt6440, and pt6930 series from power trends, a subsidiary of t exas instrum ents. not incorporating a flexible supply may limit the system?s ability to easily adapt to future versions of c641x devices. the absolute maximum ratings should not be exceeded for more than 30% of the cycle period. 12 10 8 6 4 2 0 100 110 120 130 140 150 life (yrs) junction temp (c) 10 9 8 7 6 5 4 3 2 1 life vs. temperature at 600 mhz figure 11. impact of elevated temperature on device life
sgus050a ? january 2004 ? revised march 2004 77 post office box 1443 ? houston, texas 77251?1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions ? min typ max unit v oh high-level output voltage (except pci) dv dd = min, i oh = max 2.4 v v ohp high-level output voltage (pci) [c6415/c6416 only] i ohp = ?0.5 ma, dv dd = 3.3 v 0.9dv dd ? v v ol low-level output voltage (except pci) dv dd = min, i ol = max 0.4 v v olp low-level output voltage (pci) [c6415/c6416 only] i olp = 1.5 ma, dv dd = 3.3 v 0.1dv dd ? v v i = v ss to dv dd no opposing internal resistor 10 ua i i input current (except pci) v i = v ss to dv dd opposing internal pullup resistor ? 50 100 150 ua v i = v ss to dv dd opposing internal pulldown resistor ? ?150 ?100 ?50 ua i ip input leakage current (pci) [c6415/c6416 only] 0 < v ip < dv dd = 3.3 v 10 ua emif, clkout4, clkout6, emux ?16 ma i oh high-level output current timer, utopia, tdo, gpio (excluding gp[15:9, 2, 1]), mcbsp ?8 ma pci/hpi ?0.5 ? ma emif, clkout4, clkout6, emux 16 ma i ol low-level output current timer, utopia, tdo, gpio (excluding gp[15:9, 2, 1]), mcbsp 8 ma pci/hpi 1.5 ? ma i oz off-state output current v o = dv dd or 0 v 10 ua i cdd core supply current # cv dd = 1.4 v, cpu clock = 600 mhz 750 ma i ddd i/o supply current # dv dd = 3.3 v, cpu clock = 600 mhz 125 ma c i input capacitance 12 pf c o output capacitance 12 pf ? for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions tabl e. ? applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. pci input leakage currents include hi-z output leakage for all bidirectional buffers with 3-state outputs. ? these rated numbers are from the pci specification version 2.3. the dc specification and ac specification are defined in tables 4-3 and 4-4, respectively. # measured with average activity (50% high/50% low power). the actual current draw is highly application-dependent. for more deta ils on core and i/o activity, refer to the tms320c6414/15/16 power consumption summary application report (literature number spra811). recommended clock and control signal transition behavior all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner.
sgus050a ? january 2004 ? revised march 2004 78 post office box 1443 ? houston, texas 77251?1443 parameter measurement information transmission line 4.0 pf 1.85 pf z0 = 50 (see note) tester pin electronics data sheet timing reference point output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmiss ion line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line eff ect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or l onger) from the data sheet timings. 42 3.5 nh device pin (see note) input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin . figure 12. test load circuit for ac timing measurements the tester load circuit is for characterization and measurement of ac timing signals. this load does not indicate the maximum load the device is capable of driving. signal transition levels all input and output timing parameters are referenced to 1.5 v for both ?0? and ?1? logic levels. v ref = 1.5 v figure 13. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks, v ilp max and v ihp min for pci input clocks, and v olp max and v ohp min for pci output clocks. v ref = v il max (or v ol max or v ref = v ih min (or v oh min or v ihp min or v ohp min) v ilp max or v olp max) figure 14. rise and fall transition time voltage reference levels signal transition rates all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns).
sgus050a ? january 2004 ? revised march 2004 79 post office box 1443 ? houston, texas 77251?1443 parameter measurement information (continued) timing parameters and board routing analysis the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. if needed, external logic hardware such as buf fers may be used to compensate any timing differences. for inputs, timing is most impacted by the round-trip propagation delay from the dsp to the external device and from the external device to the dsp. this round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see table 34 and figure 15). figure 15 represents a general transfer between the dsp and an external device. the figure also represents board route delays and how they are perceived by the dsp and the external device. table 34. board-level timings example (see figure 15) no. description 1 clock route delay 2 minimum dsp hold time 3 minimum dsp setup time 4 external device hold time requirement 5 external device setup time requirement 6 control signal route delay 7 external device hold time 8 external device access time 9 dsp hold time requirement 10 dsp setup time requirement 11 data route delay 1 2 3 4 5 6 7 8 10 11 eclkoutx (output from dsp) eclkoutx (input to external device) control signals ? (output from dsp) control signals (input to external device) data signals ? (output from external device) data signals ? (input to dsp) 9 ? control signals include data for writes. ? data signals are generated during reads from an external device. figure 15. board-level input/output timings
sgus050a ? january 2004 ? revised march 2004 80 post office box 1443 ? houston, texas 77251?1443 input and output clocks timing requirements for clkin ?? (see figure 16) no. pll mode x12 pll mode x6 x1 (bypass) unit no. min max min max min max unit 1 t c(clkin) cycle time, clkin 20 33.3 13.3 33.3 13.3* 33.3 ns 2 t w(clkinh) pulse duration, clkin high 0.4c* 0.4c* 0.45c* ns 3 t w(clkinl) pulse duration, clkin low 0.4c* 0.4c* 0.45c* ns 4 t t(clkin) transition time, clkin 5* 5* 1* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? for more details on the pll multiplier factors (x6, x12), see the clock pll section of this data sheet. c = clkin cycle time in ns. for example, when clkin frequency is 50 mhz, use c = 20 ns. clkin 1 2 3 4 4 figure 16. clkin timing
sgus050a ? january 2004 ? revised march 2004 81 post office box 1443 ? houston, texas 77251?1443 input and output clocks (continued) switching characteristics over recommended operating conditions for clkout4 ?? (see figure 17) no. parameter clkmode = x1, x6, x12 unit no. parameter min max unit 1 t j(cko4) period jitter, clkout4 0* 175* ps 2 t w(cko4h) pulse duration, clkout4 high 2p ? 0.7* 2p + 0.7* ns 3 t w(cko4l) pulse duration, clkout4 low 2p ? 0.7* 2p + 0.7* ns 4 t t(cko4) transition time, clkout4 1* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? ph is the high period of clkin in ns and pl is the low period of clkin in ns. p = 1/cpu clock frequency in nanoseconds (ns) ideal clock period clkout4 3 4 4 2 1 figure 17. clkout4 timing switching characteristics over recommended operating conditions for clkout6 ?? (see figure 18) no. parameter clkmode = x1, x6, x12 unit no. parameter min max unit 1 t j(cko6) period jitter, clkout6 0* 175* ps 2 t w(cko6h) pulse duration, clkout6 high 3p ? 0.7* 3p + 0.7* ns 3 t w(cko6l) pulse duration, clkout6 low 3p ? 0.7* 3p + 0.7* ns 4 t t(cko6) transition time, clkout6 1* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? ph is the high period of clkin in ns and pl is the low period of clkin in ns. p = 1/cpu clock frequency in nanoseconds (ns) ideal clock period clkout6 2 3 4 4 1 figure 18. clkout6 timing
sgus050a ? january 2004 ? revised march 2004 82 post office box 1443 ? houston, texas 77251?1443 input and output clocks (continued) timing requirements for eclkin for emifa and emifb ?? (see figure 19) no. min max unit 1 t c(eki) cycle time, eclkin 6 ?* 16p* ns 2 t w(ekih) pulse duration, eclkin high 2.7* ns 3 t w(ekil) pulse duration, eclkin low 2.7* ns 4 t t(eki) transition time, eclkin 2* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omit ted. ? minimum eclkin times are based on internal logic speed; the maximum useable speed of the emif may be lower due to ac timing requirement s. on the 7e3 and 6e3 devices, 133-mhz operation is achievable if the requirements of the emif device speed section are met. on th e 5e0 devices, 100-mhz operation is achievable if the requirements of the emif device speed section are met. eclkin 1 2 3 4 4 figure 19. eclkin timing for emifa and emifb switching characteristics over recommended operating conditions for eclkout1 for emifa and emifb modules #|| (see figure 20) no. parameter min max unit 1 t j(eko1) period jitter, eclkout1 0* 175 * ps 2 t w(eko1h) pulse duration, eclkout1 high eh ? 0.7* eh + 0.7* ns 3 t w(eko1l) pulse duration, eclkout1 low el ? 0.7* el + 0.7* ns 4 t t(eko1) transition time, eclkout1 1* ns 5 t d(ekih-eko1h) delay time, eclkin high to eclkout1 high 1* 8* ns 6 t d(ekil-eko1l) delay time, eclkin low to eclkout1 low 1* 8* ns *this parameter is not production tested. these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omit ted. # the reference points for the rise and fall transitions are measured at v ol max and v oh min. || e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa or emifb. eh is the high period of e (emif input clock period) in ns and el is the low period of e (emif input clock period) in ns for em ifa or emifb. this period jitter specification was measured with cpu/4 or cpu/6 as the source of the emif input clock.
sgus050a ? january 2004 ? revised march 2004 83 post office box 1443 ? houston, texas 77251?1443 input and output clocks (continued) ideal clock period 1 5 6 2 3 eclkin eclkout1 4 4 figure 20. eclkout1 timing for emifa and emifb modules switching characteristics over recommended operating conditions for eclkout2 for the emifa and emifb modules ?? (see figure 21) no. parameter min max unit 1 t j(eko2) period jitter, eclkout2 0* 175 ? * ps 2 t w(eko2h) pulse duration, eclkout2 high 0.5ne ? 0.7* 0.5ne + 0.7* ns 3 t w(eko2l) pulse duration, eclkout2 low 0.5ne ? 0.7* 0.5ne + 0.7* ns 4 t t(eko2) transition time, eclkout2 1* ns 5 t d(ekih-eko2h) delay time, eclkin high to eclkout2 high 1* 8* ns 6 t d(ekih-eko2l) delay time, eclkin high to eclkout2 low 1* 8* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? these c64x ? devices have two emifs (64-bit emifa and 16-bit emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omit ted. e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa or emifb. n = the emif input clock divider; n = 1, 2, or 4. ? this period jitter specification was measured with cpu/4 or cpu/6 as the source of the emif input clock. ideal clock period 5 6 eclkin eclkout2 4 4 1 2 3 figure 21. eclkout2 timing for the emifa and emifb modules
sgus050a ? january 2004 ? revised march 2004 84 post office box 1443 ? houston, texas 77251?1443 asynchronous memory timing timing requirements for asynchronous memory cycles for emifa module ?? (see figure 22 and figure 23) no. min max unit 3 t su(edv-areh) setup time, edx valid before are high 6.5 ns 4 t h(areh-edv) hold time, edx valid after are high 1 ns 6 t su(ardy-eko1h) setup time, ardy valid before eclkoutx high 3 ns 7 t h(eko1h-ardy) hold time, ardy valid after eclkoutx high 1 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. the ardy signal is only recognized two cycles before the end of the programmed strobe time and while ardy is low, the strobe time is extended cycle-by-cycle. when ardy is recognized low, the end of the strobe time is two cycles after ardy is recognized high. to use ardy as an asynchronous input, the pulse width of the ardy signal should be wide enough (e.g., pulse width = 2e) to ensure setup and hold time is met. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module ??# (see figure 22 and figure 23) no. parameter min max unit 1 t osu(selv-arel) output setup time, select signals valid to are low rs * e ? 2 ns 2 t oh(areh-seliv) output hold time, are high to select signals invalid rh * e ? 1.9 ns 5 t d(eko1h-arev) delay time, eclkoutx high to are valid 1 7 ns 8 t osu(selv-awel) output setup time, select signals valid to awe low ws * e ? 1.7 ns 9 t oh(aweh-seliv) output hold time, awe high to select signals invalid wh * e ? 1.8 ns 10 t d(eko1h-awev) delay time, eclkoutx high to awe valid 1.3 7.1 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. ? e = eclkout1 period in ns for emifa or emifb # select signals for emifa include: acex , abe[7:0] , aea[22:3], aaoe; and for emifa writes, include aed[63:0]. select signals emifb include: bcex , bbe[1:0] , bea[20:1], baoe ; and for emifb writes, include bed[15:0].
sgus050a ? january 2004 ? revised march 2004 85 post office box 1443 ? houston, texas 77251?1443 asynchronous memory timing (continued) timing requirements for asynchronous memory cycles for emifb module ?? (see figure 22 and figure 23) no. min max unit 3 t su(edv-areh) setup time, edx valid before are high 6.2 ns 4 t h(areh-edv) hold time, edx valid after are high 1 ns 6 t su(ardy-eko1h) setup time, ardy valid before eclkoutx high 3 ns 7 t h(eko1h-ardy) hold time, ardy valid after eclkoutx high 1.2 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. the ardy signal is only recognized two cycles before the end of the programmed strobe time and while ardy is low, the strobe time is extended cycle-by-cycle. when ardy is recognized low, the end of the strobe time is two cycles after ardy is recognized high. to use ardy as an asynchronous input, the pulse width of the ardy signal should be wide enough (e.g., pulse width = 2e) to ensure setup and hold time is met. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifb module ??# (see figure 22 and figure 23) no. parameter min max unit 1 t osu(selv-arel) output setup time, select signals valid to are low rs * e ? 2 ns 2 t oh(areh-seliv) output hold time, are high to select signals invalid rh * e ? 1.7 ns 5 t d(eko1h-arev) delay time, eclkoutx high to are valid 0.8 6.6 ns 8 t osu(selv-awel) output setup time, select signals valid to awe low ws * e ? 1.9 ns 9 t oh(aweh-seliv) output hold time, awe high to select signals invalid wh * e ? 1.7 ns 10 t d(eko1h-awev) delay time, eclkoutx high to awe valid 0.9 6.7 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. ? e = eclkout1 period in ns for emifa or emifb # select signals for emifa include: acex , abe[7:0] , aea[22:3], aaoe; and for emifa writes, include aed[63:0]. select signals emifb include: bcex , bbe[1:0] , bea[20:1], baoe ; and for emifb writes, include bed[15:0].
sgus050a ? january 2004 ? revised march 2004 86 post office box 1443 ? houston, texas 77251?1443 asynchronous memory timing (continued) 7 7 6 6 setup = 2 strobe = 3 not ready hold = 2 be address 1 1 1 1 5 4 5 2 2 2 2 3 read data ardy eclkoutx cex aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] aoe /sdras /soe ? are /sdcas /sads /sre ? abe[7:0] or bbe[1:0] awe /sdwe /swe ? ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. ? aoe /sdras /soe , are /sdcas /sads /sre , and awe /sdwe /swe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 22. asynchronous memory read timing for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 87 post office box 1443 ? houston, texas 77251?1443 asynchronous memory timing (continued) setup = 2 strobe = 3 not ready hold = 2 be address write data 10 10 8 8 8 8 7 7 6 6 9 9 9 9 eclkoutx cex aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] abe[7:0] or bbe[1:0] ardy aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the asynchronous memory access signals are shown as generic (aoe , are , and awe ) instead of aaoe , aare , and aawe (for emifa) and baoe , bare , and bawe (for emifb)]. ? aoe /sdras /soe , are /sdcas /sads /sre , and awe /sdwe /swe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 23. asynchronous memory write timing for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 88 post office box 1443 ? houston, texas 77251?1443 programmable synchronous interface timing timing requirements for programmable synchronous interface cycles for emifa module ? (see figure 24) no. min max unit 6 t su(edv-ekoxh) setup time, read edx valid before eclkoutx high 2 ns 7 t h(ekoxh-edv) hold time, read edx valid after eclkoutx high 1.5 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for emifa module ?? (see figure 24?figure 26) no. parameter min max unit 1 t d(ekoxh-cev) delay time, eclkoutx high to cex valid 1.3 4.9 ns 2 t d(ekoxh-bev) delay time, eclkoutx high to bex valid 5.1 ns 3 t d(ekoxh-beiv) delay time, eclkoutx high to bex invalid 1.3 ns 4 t d(ekoxh-eav) delay time, eclkoutx high to eax valid 4.9 ns 5 t d(ekoxh-eaiv) delay time, eclkoutx high to eax invalid 1.3 ns 8 t d(ekoxh-adsv) delay time, eclkoutx high to sads /sre valid 1.3 4.9 ns 9 t d(ekoxh-oev) delay time, eclkoutx high to, soe valid 1.3 4.9 ns 10 t d(ekoxh-edv) delay time, eclkoutx high to edx valid 4.9 ns 11 t d(ekoxh-ediv) delay time, eclkoutx high to edx invalid 1.3 ns 12 t d(ekoxh-wev) delay time, eclkoutx high to swe valid 1.3 4.9 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? cex assertion length (ceext): for standard sbsram or zbt sram interface, cex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, cex is active when soe is active (ceext = 1). ? function of sads /sre (renen): for standard sbsram or zbt sram interface, sads /sre acts as sads with deselect cycles (renen = 0). for fifo interface, sads /sre acts as sre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2
sgus050a ? january 2004 ? revised march 2004 89 post office box 1443 ? houston, texas 77251?1443 programmable synchronous interface timing (continued) timing requirements for programmable synchronous interface cycles for emifb module ? (see figure 24) no. min max unit 6 t su(edv-ekoxh) setup time, read edx valid before eclkoutx high 3.1 ns 7 t h(ekoxh-edv) hold time, read edx valid after eclkoutx high 1.5 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. switching characteristics over recommended operating conditions for programmable synchronous interface cycles for emifb module ?? (see figure 24?figure 26) no. parameter min max unit 1 t d(ekoxh-cev) delay time, eclkoutx high to cex valid 1.3 6.4 ns 2 t d(ekoxh-bev) delay time, eclkoutx high to bex valid 6.4 ns 3 t d(ekoxh-beiv) delay time, eclkoutx high to bex invalid 1.3 ns 4 t d(ekoxh-eav) delay time, eclkoutx high to eax valid 6.4 ns 5 t d(ekoxh-eaiv) delay time, eclkoutx high to eax invalid 1.3 ns 8 t d(ekoxh-adsv) delay time, eclkoutx high to sads /sre valid 1.3 6.4 ns 9 t d(ekoxh-oev) delay time, eclkoutx high to, soe valid 1.3 6.4 ns 10 t d(ekoxh-edv) delay time, eclkoutx high to edx valid 6.4 ns 11 t d(ekoxh-ediv) delay time, eclkoutx high to edx invalid 1.3 ns 12 t d(ekoxh-wev) delay time, eclkoutx high to swe valid 1.3 6.4 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. ? the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? cex assertion length (ceext): for standard sbsram or zbt sram interface, cex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, cex is active when soe is active (ceext = 1). ? function of sads /sre (renen): for standard sbsram or zbt sram interface, sads /sre acts as sads with deselect cycles (renen = 0). for fifo interface, sads /sre acts as sre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2
sgus050a ? january 2004 ? revised march 2004 90 post office box 1443 ? houston, texas 77251?1443 programmable synchronous interface timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] are /sdcas /sads /sre aoe /sdras /soe awe /sdwe /swe be1 be2 be3 be4 q1 q2 q3 q4 9 1 4 5 8 9 6 7 3 1 2 be1 be2 be3 be4 ea1 ea2 ea4 8 read latency = 2 ea3 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. ? the read latency and the length of cex assertion are programmable via the syncrl and ceext fields, respectively, in the emifx ce space secondary control register (cexsec). in this figure, syncrl = 2 and ceext = 0. the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? cex assertion length (ceext): for standard sbsram or zbt sram interface, cex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, cex is active when soe is active (ceext = 1). ? function of sads /sre (renen): for standard sbsram or zbt sram interface, sads /sre acts as sads with deselect cycles (renen = 0). for fifo interface, sads /sre acts as sre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2 ? are /sdcas /sads /sre , aoe /sdras /soe , and awe /sdwe /swe operate as sads /sre , soe , and swe , respectively, during programmable synchronous interface accesses. figure 24. programmable synchronous interface read timing for emifa and emifb (with read latency = 2) ??
sgus050a ? january 2004 ? revised march 2004 91 post office box 1443 ? houston, texas 77251?1443 programmable synchronous interface timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] are /sdcas /sads /sre ? aoe /sdras /soe ? awe /sdwe /swe ? be1 be2 be3 be4 q1 q2 q3 q4 12 11 3 1 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. ? the write latency and the length of cex assertion are programmable via the syncwl and ceext fields, respectively, in the emifx ce space secondary control register (cexsec). in this figure, syncwl = 0 and ceext = 0. the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? cex assertion length (ceext): for standard sbsram or zbt sram interface, cex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, cex is active when soe is active (ceext = 1). ? function of sads /sre (renen): for standard sbsram or zbt sram interface, sads /sre acts as sads with deselect cycles (renen = 0). for fifo interface, sads /sre acts as sre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2 ? are /sdcas /sads /sre , aoe /sdras /soe , and awe /sdwe /swe operate as sads /sre , soe , and swe , respectively, during programmable synchronous interface accesses. figure 25. programmable synchronous interface write timing for emifa and emifb (with write latency = 0) ??
sgus050a ? january 2004 ? revised march 2004 92 post office box 1443 ? houston, texas 77251?1443 programmable synchronous interface timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] are /sdcas /sads /sre ? aoe /sdras /soe ? awe /sdwe /swe ? be1 be2 be3 be4 q1 q2 q3 11 3 12 10 4 2 1 8 5 8 ea1 ea2 ea3 ea4 10 write latency = 1 ? 1 q4 12 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the programmable synchronous interface access signals are shown as generic (sads /sre , soe , and swe ) instead of asads /asre , asoe , and aswe (for emifa) and bsads /bsre , bsoe , and bswe (for emifb)]. ? the write latency and the length of cex assertion are programmable via the syncwl and ceext fields, respectively, in the emifx ce space secondary control register (cexsec). in this figure, syncwl = 1 and ceext = 0. the following parameters are programmable via the emif ce space secondary control register (cexsec): ? read latency (syncrl): 0-, 1-, 2-, or 3-cycle read latency ? write latency (syncwl): 0-, 1-, 2-, or 3-cycle write latency ? cex assertion length (ceext): for standard sbsram or zbt sram interface, cex goes inactive after the final command has been issued (ceext = 0). for synchronous fifo interface with glue, cex is active when soe is active (ceext = 1). ? function of sads /sre (renen): for standard sbsram or zbt sram interface, sads /sre acts as sads with deselect cycles (renen = 0). for fifo interface, sads /sre acts as sre with no deselect cycles (renen = 1). ? synchronization clock (sncclk): synchronized to eclkout1 or eclkout2 ? are /sdcas /sads /sre , aoe /sdras /soe , and awe /sdwe /swe operate as sads /sre , soe , and swe , respectively, during programmable synchronous interface accesses. figure 26. programmable synchronous interface write timing for emifa and emifb (with write latency = 1) ??
sgus050a ? january 2004 ? revised march 2004 93 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing timing requirements for synchronous dram cycles for emifa module ? (see figure 27) no. min max unit 6 t su(edv-eko1h) setup time, read edx valid before eclkoutx high 0.6 ns 7 t h(eko1h-edv) hold time, read edx valid after eclkoutx high 1.8 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. switching characteristics over recommended operating conditions for synchronous dram cycles for emifa module ? (see figure 27?figure 34) no. parameter min max unit 1 t d(eko1h-cev) delay time, eclkoutx high to cex valid 1.3 4.9 ns 2 t d(eko1h-bev) delay time, eclkoutx high to bex valid 4.9 ns 3 t d(eko1h-beiv) delay time, eclkoutx high to bex invalid 1.3 ns 4 t d(eko1h-eav) delay time, eclkoutx high to eax valid 4.9 ns 5 t d(eko1h-eaiv) delay time, eclkoutx high to eax invalid 1.3 ns 8 t d(eko1h-casv) delay time, eclkoutx high to sdcas valid 1.3 4.9 ns 9 t d(eko1h-edv) delay time, eclkoutx high to edx valid 4.9 ns 10 t d(eko1h-ediv) delay time, eclkoutx high to edx invalid 1.3 ns 11 t d(eko1h-wev) delay time, eclkoutx high to sdwe valid 1.3 4.9 ns 12 t d(eko1h-ras) delay time, eclkoutx high to sdras valid 1.3 4.9 ns 13 t d(eko1h-ackev) delay time, eclkoutx high to asdcke valid (emifa only) 1.3 4.9 ns 14 t d(eko1h-pdtv) delay time, eclkoutx high to pdt valid 1.3 4.9 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)].
sgus050a ? january 2004 ? revised march 2004 94 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) timing requirements for synchronous dram cycles for emifb module ? (see figure 27) no. min max unit 6 t su(edv-eko1h) setup time, read edx valid before eclkoutx high 2.1 ns 7 t h(eko1h-edv) hold time, read edx valid after eclkoutx high 2.5 ns ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. switching characteristics over recommended operating conditions for synchronous dram cycles for emifb module ? (see figure 27?figure 34) no. parameter min max unit 1 t d(eko1h-cev) delay time, eclkoutx high to cex valid 1.3 6.4 ns 2 t d(eko1h-bev) delay time, eclkoutx high to bex valid 6.4 ns 3 t d(eko1h-beiv) delay time, eclkoutx high to bex invalid 1.3 ns 4 t d(eko1h-eav) delay time, eclkoutx high to eax valid 6.4 ns 5 t d(eko1h-eaiv) delay time, eclkoutx high to eax invalid 1.3 ns 8 t d(eko1h-casv) delay time, eclkoutx high to sdcas valid 1.3 6.4 ns 9 t d(eko1h-edv) delay time, eclkoutx high to edx valid 6.4 ns 10 t d(eko1h-ediv) delay time, eclkoutx high to edx invalid 1.3 ns 11 t d(eko1h-wev) delay time, eclkoutx high to sdwe valid 1.3 6.4 ns 12 t d(eko1h-ras) delay time, eclkoutx high to sdras valid 1.3 6.4 ns 13 t d(eko1h-ackev) delay time, eclkoutx high to asdcke valid (emifa only) 1.3* 6.4* ns 14 t d(eko1h-pdtv) delay time, eclkoutx high to pdt valid 1.3 6.4 ns *this parameter is not production tested. ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)].
sgus050a ? january 2004 ? revised march 2004 95 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[12:3] or bea[10:1] aed[63:0] or bed[15:0] aea13 or bea11 aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? aea[22:14] or bea[20:12] be1 be2 be3 be4 bank column d1 d2 d3 d4 8 7 6 5 5 5 1 3 2 8 4 4 4 1 read pdt 14 14 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. pdt signal is only asserted when the edma is in pdt mode (set the pdts bit to 1 in the edma options parameter ram). for pdt read, data is not latched into emif. the pdtrl field in the pdt control register (pdtctl) configures the latency of the pdt signal with respect to the data phase of a read transaction. the latency of the pdt signal for a read can be programmed to 0, 1, 2, or 3 by setting pdtrl to 00, 01, 10, or 11, respectively. pdtrl equals 00 (zero latency) in figure 27. figure 27. sdram read command (cas latency 3) for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 96 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[12:3] or bea[10:1] aed[63:0] or bed[15:0] aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? aea13 or bea11 aea[22:14] or bea[20:12] be1 be2 be3 be4 bank column d1 d2 d3 d4 11 8 9 5 5 5 4 2 11 8 9 4 4 2 1 10 3 4 write pdt 14 14 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. pdt signal is only asserted when the edma is in pdt mode (set the pdtd bit to 1 in the edma options parameter ram). for pdt write, data is not driven (in high-z). the pdtwl field in the pdt control register (pdtctl) configures the latency of the pdt signal with respect to the data phase of a write transaction. the latency of the pdt signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting pdtwl to 00, 01, 10, or 11, respectively. pdtwl equals 00 (zero latency) in figure 28. figure 28. sdram write command for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 97 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0 ] aea[22:14] or bea[20:12] aed[63:0] or bed[15:0] aea13 or bea11 aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? bank activate row address row address 12 5 5 5 1 aea[12:3] or bea[10:1] actv 12 4 4 4 1 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 29. sdram actv command for emifa and emfb ?
sgus050a ? january 2004 ? revised march 2004 98 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:14, 12:3] or bea[20:12, 10:1] aed[63:0] or bed[15:0] aea13 or bea11 aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? 11 12 5 1 dcab 11 12 4 1 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 30. sdram dcab command for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 99 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:14] or bea[20:12] aed[63:0] or bed[15:0] aea13 or bea11 aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? aea[12:3] or bea[10:1] bank 11 12 5 5 1 deac 11 12 4 4 1 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 31. sdram deac command for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 100 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:14, 12:3] or bea[20:12, 10:1] aed[63:0] or bed[15:0] aea13 or bea11 aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? 8 12 1 refr 8 12 1 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 32. sdram refr command for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 101 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) eclkoutx cex abe[7:0] or bbe[1:0] aea[22:3] or bea[20:1] aed[63:0] or bed[15:0] aoe /sdras /soe ? are /sdcas /sads /sre ? awe /sdwe /swe ? mrs value 11 8 12 5 1 mrs 11 8 12 4 1 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 33. sdram mrs command for emifa and emifb ?
sgus050a ? january 2004 ? revised march 2004 102 post office box 1443 ? houston, texas 77251?1443 synchronous dram timing (continued) end self-refresh self refresh 13 13 aeclkoutx acex abe[7:0] aea[22:14, 12:3] aea13 aed[63:0] aaoe /asdras /asoe ? aare /asdcas /asads / asre ? aawe /asdwe /aswe ? asdcke tras cycles ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., the sync hronous dram memory access signals are shown as generic ( sdcas , sdwe , and sdras ) instead of asdcas , asdwe , and asdras (for emifa) and bsdcas , bsdwe , and bsdras (for emifb)]. ? aare /asdcas /asads /asre , aawe /asdwe /aswe , and aaoe /asdras /asoe operate as asdcas , asdwe , and asdras , respectively, during sdram accesses. figure 34. sdram self-refresh timing for emifa only ?
sgus050a ? january 2004 ? revised march 2004 103 post office box 1443 ? houston, texas 77251?1443 hold /holda timing timing requirements for the hold /holda cycles for emifa and emifb modules ? (see figure 35) no. min max unit 3 t oh(holdal-holdl) hold time, hold low after holda low e* ns *this parameter is not production tested. ? e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa or emifb. switching characteristics over recommended operating conditions for the hold /holda cycles for emifa and emifb modules ?? (see figure 35) no. parameter min max unit 1 t d(holdl-emhz) delay time, hold low to emif bus high impedance 2e* ? * ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0* 2e* ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 2e* 7e* ns 5 t d(emlz-holdah) delay time, emif bus low impedance to holda high 0* 2e* ns 6 t d(holdl-ekohz) delay time, hold low to eclkoutx high impedance 2e* ? * ns 7 t d(holdh-ekolz) delay time, hold high to eclkoutx low impedance 2e* 7e* ns *this parameter is not production tested. ? e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa or emifb. ? for emifa, emif bus consists of: ace[3:0] , abe[7:0] , aed[63:0], aea[22:3], aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe , asdcke, asoe3 , and apdt . for emifb, emif bus consists of: bce[3:0] , bbe[1:0] , bed[15:0], bea[20:1], bare /bsdcas /bsads /bsre , baoe /bsdras /bsoe , and bawe /bsdwe /bswe , bsoe3 , and bpdt . the ekxhz bits in the emif global control register (gblctl) determine the state of the eclkoutx signals during holda . if ekxhz = 0, eclkoutx continues clocking during hold mode. if ekxhz = 1, eclkoutx goes to high impedance during hold mode, as shown in figure 35. ? all pending emif transactions are allowed to complete before holda is asserted. if no bus transactions are occurring, then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. hold holda emif bus ? dsp owns bus external requestor owns bus dsp owns bus c64x c64x 1 3 25 4 eclkoutx ? (ekxhz = 0) eclkoutx ? (ekxhz = 1) 6 7 ? for emifa, emif bus consists of: ace[3:0] , abe[7:0] , aed[63:0], aea[22:3], aare /asdcas /asads /asre , aaoe /asdras /asoe , and aawe /asdwe /aswe , asdcke, asoe3 , and apdt . for emifb, emif bus consists of: bce[3:0] , bbe[1:0] , bed[15:0], bea[20:1], bare /bsdcas /bsads /bsre , baoe /bsdras /bsoe , and bawe /bsdwe /bswe , bsoe3 , and bpdt . ? the ekxhz bits in the emif global control register (gblctl) determine the state of the eclkoutx signals during holda . if ekxhz = 0, eclkoutx continues clocking during hold mode. if ekxhz = 1, eclkoutx goes to high impedance during hold mode, as shown in figure 35. figure 35. hold /holda timing for emifa and emifb
sgus050a ? january 2004 ? revised march 2004 104 post office box 1443 ? houston, texas 77251?1443 busreq timing switching characteristics over recommended operating conditions for the busreq cycles for emifa and emifb modules (see figure 36) no. parameter min max unit 1 t d(aeko1h-abusrv) delay time, aeclkoutx high to abusreq valid 1 5.5 ns 2 t d(beko1h-bbusrv) delay time, beclkoutx high to bbusreq valid 0.9 5.5 ns eclkoutx 1 abusreq 1 2 2 bbusreq figure 36. busreq timing for emifa and emifb
sgus050a ? january 2004 ? revised march 2004 105 post office box 1443 ? houston, texas 77251?1443 reset timing timing requirements for reset ? (see figure 37) no. min max unit 1 t w(rst) width of the reset pulse (pll stable) ? 10p* ns 1 t w(rst) width of the reset pulse (pll needs to sync up) 250* s 16 t su(boot) setup time, boot configuration bits valid before reset high ? 4p* ns 17 t h(boot) hold time, boot configuration bits valid after reset high ? 4p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? this parameter applies to clkmode x1 when clkin is stable, and applies to clkmode x6, x12 when clkin and pll are stable. this parameter applies to clkmode x6, x12 only (it does not apply to clkmode x1). the reset signal is not connected internally to the clock pll circuit. the pll, however, may need up to 250 s to stabilize following device power up or after pll configuration has been changed. during that time, reset must be asserted to ensure proper device operation. see the clock pll section for pll lock times. ? emifb address pins bea[20:13, 11, 7] are the boot configuration pins during device reset. switching characteristics over recommended operating conditions during reset ?#|| (see figure 37) no. parameter min max unit 2 t d(rstl-ecki) delay time, reset low to eclkin synchronized internally 2e* 3p + 20e* ns 3 t d(rsth-ecki) delay time, reset high to eclkin synchronized internally 2e* 8p + 20e* ns 4 t d(rstl-ecko1hz) delay time, reset low to eclkout1 high impedance 2e* ns 5 t d(rsth-ecko1v) delay time, reset high to eclkout1 valid 8p + 20e* ns 6 t d(rstl-emifzhz) delay time, reset low to emif z high impedance 2e* 3p + 4e* ns 7 t d(rsth-emifzv) delay time, reset high to emif z valid 16e* 8p + 20e* ns 8 t d(rstl-emifhiv) delay time, reset low to emif high group invalid 2e* ns 9 t d(rsth-emifhv) delay time, reset high to emif high group valid 8p + 20e* ns 10 t d(rstl-emifliv) delay time, reset low to emif low group invalid 2e* ns 11 t d(rsth-emiflv) delay time, reset high to emif low group valid 8p + 20e* ns 12 t d(rstl-lowiv) delay time, reset low to low group invalid 0* ns 13 t d(rsth-lowv) delay time, reset high to low group valid 11p* ns 14 t d(rstl-zhz) delay time, reset low to z group high impedance 0* ns 15 t d(rsth-zv) delay time, reset high to z group valid 2p* 8p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. # e = the emif input clock (eclkin, cpu/4 clock, or cpu/6 clock) period in ns for emifa or emifb. || emif z group consists of: aea[22:3], bea[20:1], aed[63:0], bed[15:0], ce[3:0] , abe[7:0] , bbe[1:0] , are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe , soe3 , asdcke, and pdt . emif high group consists of: aholda and bholda (when the corresponding hold input is high) emif low group consists of: abusreq and bbusreq; aholda and bholda (when the corresponding hold input is low) low group consists of: xsp_cs, clkx2/xsp_clk, and dx2/xsp_do; all of which apply only when pci eeprom (bea13) is enabled (with pci_en = 1 and mcbsp2_en = 0). otherwise, the clkx2/xsp_clk and dx2/xsp_do pins are in the z group. for more details on the pci configuration pins, see the device configurations section of this data sheet. z group consists of: hd[31:0]/ad[31:0], clkx0, clkx1/uraddr4, clkx2/xsp_clk, fsx0, fsx1/uxaddr3, fsx2, dx0, dx1/uxaddr4, dx2/xsp_do, clkr0, clkr1/uraddr2, clkr2, fsr0, fsr1/uxaddr2, fsr2, tout0, tout1, tout2, gp[8:0], gp10/pcbe3 , hr/w /pcbe2 , hds2 /pcbe1 , pcbe0 , gp13/pinta , gp11/preq , hds1 /pserr , hcs /pperr , hcntl1/pdevsel , has /ppar, hcntl0/pstop , hhwil/ptrdy (16-bit hpi mode only), hrdy /pirdy , hint /pframe , uxdata[7:0], uxsoc, uxclav, and urclav.
sgus050a ? january 2004 ? revised march 2004 106 post office box 1443 ? houston, texas 77251?1443 reset timing (continued) eclkout2 17 14 1 clkout4 clkout6 reset eclkin low group ? z group ? boot and device configuration inputs ? 16 15 3 2 10 8 emif z group ? emif high group ? emif low group ? 11 9 7 6 13 12 eclkout1 5 4 ? these c64x ? devices have two emifs (emifa and emifb). all emifa signals are prefixed by an ?a? and all emifb signals are prefixed by a ?b?. throughout the rest of this document, in generic emif areas of discussion, the prefix ?a? or ?b? may be omitted [e.g., ecl kin, eclkout1, and eclkout2]. ? emif z group consists of: aea[22:3], bea[20:1], aed[63:0], bed[15:0], ce[3:0] , abe[7:0] , bbe[1:0] , are /sdcas /sads /sre , awe /sdwe /swe , and aoe /sdras /soe , soe3 , asdcke, and pdt . emif high group consists of: aholda and bholda (when the corresponding hold input is high) emif low group consists of: abusreq and bbusreq; aholda and bholda (when the corresponding hold input is low) low group consists of: xsp_cs, clkx2/xsp_clk, and dx2/xsp_do; all of which apply only when pci eeprom (bea13) is enabled (with pci_en = 1 and mcbsp2_en = 0). otherwise, the clkx2/xsp_clk and dx2/xsp_do pins are in the z group. for more details on the pci configuration pins, see the device configurations section of this data sheet. z group consists of: hd[31:0]/ad[31:0], clkx0, clkx1/uraddr4, clkx2/xsp_clk, fsx0, fsx1/uxaddr3, fsx2, dx0, dx1/uxaddr4, dx2/xsp_do, clkr0, clkr1/uraddr2, clkr2, fsr0, fsr1/uxaddr2, fsr2, tout0, tout1, tout2, gp[8:0], gp10/pcbe3 , hr/w /pcbe2 , hds2 /pcbe1 , pcbe0 , gp13/pinta , gp11/preq , hds1 /pserr , hcs /pperr , hcntl1/pdevsel , has /ppar, hcntl0/pstop , hhwil/ptrdy (16-bit hpi mode only), hrdy /pirdy , hint /pframe , uxdata[7:0], uxsoc, uxclav, and urclav. if bea[20:13, 11, 7] and hd5/ad5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. ? boot and device configurations inputs (during reset) include: emifb address pins bea[20:13, 11, 7] and hd5/ad5. the pci_en pin must be driven valid at all times and the user must not switch values throughout device operation. the mcbsp2_en pin must be driven valid at all times and the user can switch values throughout device operation. figure 37. reset timing ?
sgus050a ? january 2004 ? revised march 2004 107 post office box 1443 ? houston, texas 77251?1443 external interrupt timing timing requirements for external interrupts ? (see figure 38) min max 1 t w(ilow) width of the nmi interrupt pulse low 4p* ns 1 t w(ilow) width of the ext_int interrupt pulse low 8p* ns 2 t w(ihigh) width of the nmi interrupt pulse high 4p* ns 2 t w(ihigh) width of the ext_int interrupt pulse high 8p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. 2 1 ext_intx, nmi figure 38. external/nmi interrupt timing
sgus050a ? january 2004 ? revised march 2004 108 post office box 1443 ? houston, texas 77251?1443 host-port interface (hpi) timing timing requirements for host-port interface cycles ?? (see figure 39 through figure 46) no. min max unit 1 t su(selv-hstbl) setup time, select signals valid before hstrobe low 5 ns 2 t h(hstbl-selv) hold time, select signals valid after hstrobe low 2.4 ns 3 t w(hstbl) pulse duration, hstrobe low 4p ? * ns 4 t w(hstbh) pulse duration, hstrobe high between consecutive accesses 4p* ns 10 t su(selv-hasl) setup time, select signals valid before has low 5 ns 11 t h(hasl-selv) hold time, select signals valid after has low 2 ns 12 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 13 t h(hstbh-hdv) hold time, host data valid after hstrobe high 2.8 ns 14 t h(hrdyl-hstbl) hold time, hstrobe low after hrdy low. hstrobe should not be inactivated until hrdy is active (low); otherwise, hpi writes will not complete properly. 2* ns 18 t su(hasl-hstbl) setup time, has low before hstrobe low 2 ns 19 t h(hstbl-hasl) hold time, has low after hstrobe low 2.1 ns *this parameter is not production tested. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. select signals include: hcntl[1:0] and hr/w . for hpi16 mode only, select signals also include hhwil. ? select the parameter value of 4p or 12.5 ns, whichever is greater. switching characteristics over recommended operating conditions during host-port interface cycles ?? (see figure 39 through figure 46) no. parameter min max unit 6 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high # 1.3 4p + 8 ns 7 t d(hstbl-hdlz) delay time, hstrobe low to hd low impedance for an hpi read 2* ns 8 t d(hdv-hrdyl) delay time, hd valid to hrdy low ?3 ns 9 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 1.5 ns 15 t d(hstbh-hdhz) delay time, hstrobe high to hd high impedance 12* ns 16 t d(hstbl-hdv) delay time, hstrobe low to hd valid (hpi16 only) 4p + 8 ns *this parameter is not production tested. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. # this parameter is used during hpid reads and writes. for reads, at the beginning of a word transfer (hpi32) or the first half-word t ransfer (hpi16) on the falling edge of hstrobe , the hpi sends the request to the edma internal address generation hardware, and hrdy remains high until the edma internal address generation hardware loads the requested data into hpid. for writes, hrdy goes high if the internal write buffer is full.
sgus050a ? january 2004 ? revised march 2004 109 post office box 1443 ? houston, texas 77251?1443 host-port interface (hpi) timing (continued) 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy 3 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 39. hpi16 read timing (has not used, tied high) has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 40. hpi16 read timing (has used)
sgus050a ? january 2004 ? revised march 2004 110 post office box 1443 ? houston, texas 77251?1443 host-port interface (hpi) timing (continued) 1st half-word 2nd half-word 13 12 13 12 4 14 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 3 6 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 41. hpi16 write timing (has not used, tied high) 1st half-word 2nd half-word 13 12 13 12 4 14 3 11 10 11 10 11 10 11 10 11 10 11 10 has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 19 19 18 18 6 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 42. hpi16 write timing (has used)
sgus050a ? january 2004 ? revised march 2004 111 post office box 1443 ? houston, texas 77251?1443 host-port interface (hpi) timing (continued) 6 3 has hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (output) hrdy 8 9 7 2 1 2 1 15 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 43. hpi32 read timing (has not used, tied high) 8 6 15 9 7 3 18 11 10 11 10 19 has ? hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (output) hrdy ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 44. hpi32 read timing (has used)
sgus050a ? january 2004 ? revised march 2004 112 post office box 1443 ? houston, texas 77251?1443 host-port interface (hpi) timing (continued) 13 12 14 3 2 1 2 1 has hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (input) hrdy 6 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 45. hpi32 write timing (has not used, tied high) 13 12 14 3 18 11 10 11 10 19 has ? hcntl[1:0] hr/w hstrobe ? hcs hd[31:0] (input) hrdy 6 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 46. hpi32 write timing (has used)
sgus050a ? january 2004 ? revised march 2004 113 post office box 1443 ? houston, texas 77251?1443 peripheral component interconnect (pci) timing [c6415 and c6416 only] timing requirements for pclk ?? (see figure 47) no. min max unit 1 t c(pclk) cycle time, pclk 30 (or 8p )* ns 2 t w(pclkh) pulse duration, pclk high 11* ns 3 t w(pclkl) pulse duration, pclk low 11* ns 4 t sr(pclk) ? v/ ? t slew rate, pclk 1* 4* v/ns *this parameter is not production tested. ? for 3.3-v operation, the reference points for the rise and fall transitions are measured at v ilp max and v ihp min. ? p = 1/cpu clock frequency in ns. for example when running parts at 600 mhz, use p = 1.67 ns. select the parameter value of 30 ns or 8p, whichever is greater. pclk 1 2 3 4 4 0.4 dv dd v min peak to peak for 3.3v signaling figure 47. pclk timing timing requirements for pci reset (see figure 48) no. min max unit 1 t w(prst) pulse duration, prst 1* ms 2 t su(pclka-prsth) setup time, pclk active before prst high 100* s *this parameter is not production tested. prst pclk 2 1 figure 48. pci reset (prst ) timing
sgus050a ? january 2004 ? revised march 2004 114 post office box 1443 ? houston, texas 77251?1443 peripheral component interconnect (pci) timing [c6415 and c6416 only] (continued) timing requirements for pci inputs (see figure 49) no. min max unit 5 t su(iv-pclkh) setup time, input valid before pclk high 7 ns 6 t h(iv-pclkh) hold time, input valid after pclk high 0 ns switching characteristics over recommended operating conditions for pci outputs (see figure 49) no. parameter min max unit 1 t d(pclkh-ov) delay time, pclk high to output valid 11 ns 2 t d(pclkh-oiv) delay time, pclk high to output invalid 2 ns 3 t d(pclkh-olz) delay time, pclk high to output low impedance 2* ns 4 t d(pclkh-ohz) delay time, pclk high to output high impedance 28* ns *this parameter is not production tested. valid pclk 5 pci output pci input 3 valid 2 6 1 4 figure 49. pci input/output timing
sgus050a ? january 2004 ? revised march 2004 115 post office box 1443 ? houston, texas 77251?1443 peripheral component interconnect (pci) timing [c6415 and c6416 only] (continued) timing requirements for serial eeprom interface (see figure 50) no. min max unit 8 t su(div-clkh) setup time, xsp_di valid before xsp_clk high 50* ns 9 t h(clkh-div) hold time, xsp_di valid after xsp_clk high 0* ns *this parameter is not production tested. switching characteristics over recommended operating conditions for serial eeprom interface ? (see figure 50) no. parameter min typ max unit 1 t w(csl) pulse duration, xsp_cs low 4092p ns 2 t d(clkl-csl) delay time, xsp_clk low to xsp_cs low 0 ns 3 t d(csh-clkh) delay time, xsp_cs high to xsp_clk high 2046p ns 4 t w(clkh) pulse duration, xsp_clk high 2046p ns 5 t w(clkl) pulse duration, xsp_clk low 2046p ns 6 t osu(dov-clkh) output setup time, xsp_do valid after xsp_clk high 2046p ns 7 t oh(clkh-dov) output hold time, xsp_do valid after xsp_clk high 2046p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. 9 8 7 6 3 2 5 4 1 xsp_cs xsp_clk xsp_do xsp_di figure 50. pci serial eeprom interface timing
sgus050a ? january 2004 ? revised march 2004 116 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing timing requirements for mcbsp ? (see figure 51) no. min max unit 2 t c(ckrx) cycle time, clkr/x clkr/x ext 6.67 ? * ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext 0.5t c(ckrx) ? 1 * ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 1.3 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int 6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 0.9 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr int 3 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 3.1 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 1.3 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns *this parameter is not production tested. ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timi ng requirements. this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the reasonable range of 40/60 duty cyc le.
sgus050a ? january 2004 ? revised march 2004 117 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) switching characteristics over recommended operating conditions for mcbsp ?? (see figure 51) no. parameter min max unit 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 1.4 10 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 6.67 * ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 1 ? * c + 1 ? * ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ?2.1 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int ?1.7 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 1.7 9 ns 12 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit clkx int ?3.9* 4* ns 12 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high clkx ext ?2.1* 9* ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx int ?3.9 + d1 # 4 + d2 # ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext ?2.1 + d1 # 9 + d2 # ns 14 t d(fxh-dxv) delay time, fsx high to dx valid fsx int ?2.3 5.6 ns 14 t d(fxh-dxv) only applies when in data delay 0 (xdatdly = 00b) mode fsx ext 1.9 9 ns *this parameter is not production tested. ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? minimum delay times also represent minimum output hold times. minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timi ng requirements. ? c = h or l s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see ? footnote above). # extra delay from clkx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 4p, d2 = 8p
sgus050a ? january 2004 ? revised march 2004 118 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 51. mcbsp timing
sgus050a ? january 2004 ? revised march 2004 119 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) timing requirements for fsr when gsync = 1 (see figure 52) no. min max unit 1 t su(frh-cksh) setup time, fsr high before clks high 4* ns 2 t h(cksh-frh) hold time, fsr high after clks high 4* ns *this parameter is not production tested. 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 52. fsr timing when gsync = 1 timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 53) no. master slave unit no. min max min max unit 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 12p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 24p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1.
sgus050a ? january 2004 ? revised march 2004 120 post office box 1443 ? houston, texas 77251?1443 switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 53) no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t ? 2 t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l ? 2* l + 3* ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2 4 12p + 2.8 20p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l ? 2* l + 3* ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 4p + 3* 12p + 17* ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 8p + 1.8 16p + 17 ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 53. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0
sgus050a ? january 2004 ? revised march 2004 121 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 54) no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12* 2 ? 12p* ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4* 5 + 24p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 54) no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l ? 2* l + 3* ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 2* t + 3* ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2* 4* 12p + 4* 20p + 17* ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low ?2* 4* 12p + 3* 20p + 17* ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2* h + 4* 8p + 2* 16p + 17* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 54. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0
sgus050a ? january 2004 ? revised march 2004 122 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 55) no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12* 2 ? 12p* ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4* 5 + 24p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 55) no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t ? 2* t + 3* ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h ? 2* h + 3* ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ?2* 4* 12p + 4* 20p + 17* ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h ? 2* h + 3* ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 4p + 3* 12p + 17* ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 8p + 2* 16p + 17* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 55. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1
sgus050a ? january 2004 ? revised march 2004 123 post office box 1443 ? houston, texas 77251?1443 multichannel buffered serial port (mcbsp) timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 56) no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12* 2 ? 12p* ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4* 5 + 24p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 56) no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h ? 2* h + 3* ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 2* t + 1* ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ?2* 4* 12p + 4* 20p + 17* ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high ?2* 4* 12p + 3* 20p + 17* ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2* l + 4* 8p + 2* 16p + 17* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? for all spi slave modes, clkg is programmed as 1/4 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 4p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 56. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1
sgus050a ? january 2004 ? revised march 2004 124 post office box 1443 ? houston, texas 77251?1443 utopia slave timing [c6415 and c6416 only] timing requirements for uxclk ? (see figure 57) no. min max unit 1 t c(uxck) cycle time, uxclk 20* ns 2 t w(uxckh) pulse duration, uxclk high 0.4t c(uxck) * 0.6t c(uxck) * ns 3 t w(uxckl) pulse duration, uxclk low 0.4t c(uxck) * 0.6t c(uxck) * ns 4 t t(uxck) transition time, uxclk 2* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. uxclk 1 2 3 4 4 figure 57. uxclk timing timing requirements for urclk ? (see figure 58) no. min max unit 1 t c(urck) cycle time, urclk 20* ns 2 t w(urckh) pulse duration, urclk high 0.4t c(urck) * 0.6t c(urck) * ns 3 t w(urckl) pulse duration, urclk low 0.4t c(urck) * 0.6t c(urck) * ns 4 t t(urck) transition time, urclk 2* ns *this parameter is not production tested. ? the reference points for the rise and fall transitions are measured at v il max and v ih min. urclk 1 2 3 4 4 figure 58. urclk timing
sgus050a ? january 2004 ? revised march 2004 125 post office box 1443 ? houston, texas 77251?1443 utopia slave timing [c6415 and c6416 only] (continued) timing requirements for utopia slave transmit (see figure 59) no. min max unit 2 t su(uxav-uxch) setup time, uxaddr valid before uxclk high 4 ns 3 t h(uxch-uxav) hold time, uxaddr valid after uxclk high 1 ns 8 t su(uxenbl-uxch) setup time, uxenb low before uxclk high 4 ns 9 t h(uxch-uxenbl) hold time, uxenb low after uxclk high 1 ns switching characteristics over recommended operating conditions for utopia slave transmit (see figure 59) no. parameter min max unit 1 t d(uxch-uxdv) delay time, uxclk high to uxdata valid 3 12 ns 4 t d(uxch-uxclav) delay time, uxclk high to uxclav driven active value 3 12 ns 5 t d(uxch-uxclavl) delay time, uxclk high to uxclav driven inactive low 3* 12* ns 6 t d(uxch-uxclavhz) delay time, uxclk high to uxclav going hi-z 9* 18.5* ns 7 t w(uxclavl-uxclavhz) pulse duration (low), uxclav low to uxclav hi-z 3* ns 10 t d(uxch-uxsv) delay time, uxclk high to uxsoc valid 3 12 ns *this parameter is not production tested. p47 p48 h1 n 0x1f n 0x1f n + 1 0x1f n n 10 8 4 3 2 1 uxclk uxdata[7:0] uxaddr[4:0] uxclav uxenb uxsoc 9 p46 p45 0 x1f the utopia slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the uxclav and uxsoc signals). ? 5 6 7 figure 59. utopia slave transmit timing ?
sgus050a ? january 2004 ? revised march 2004 126 post office box 1443 ? houston, texas 77251?1443 utopia slave timing [c6415 and c6416 only] (continued) timing requirements for utopia slave receive (see figure 60) no. min max unit 1 t su(urdv-urch) setup time, urdata valid before urclk high 4 ns 2 t h(urch-urdv) hold time, urdata valid after urclk high 1 ns 3 t su(urav-urch) setup time, uraddr valid before urclk high 4 ns 4 t h(urch-urav) hold time, uraddr valid after urclk high 1 ns 9 t su(urenbl-urch) setup time, urenb low before urclk high 4 ns 10 t h(urch-urenbl) hold time, urenb low after urclk high 1 ns 11 t su(ursh-urch) setup time, ursoc high before urclk high 4 ns 12 t h(urch-ursh) hold time, ursoc high after urclk high 1 ns switching characteristics over recommended operating conditions for utopia slave receive (see figure 60) no. parameter min max unit 5 t d(urch-urclav) delay time, urclk high to urclav driven active value 3 12 ns 6 t d(urch-urclavl) delay time, urclk high to urclav driven inactive low 3* 12* ns 7 t d(urch-urclavhz) delay time, urclk high to urclav going hi-z 9* 18.5* ns 8 t w(urclavl-urclavhz) pulse duration (low), urclav low to urclav hi-z 3* ns *this parameter is not production tested. p48 h1 h2 h3 n 0x1f n+1 0x1f n+2 0x1f n n+1 n+2 12 11 9 10 5 4 3 2 1 urclk urdata[7:0] uraddr[4:0] urclav urenb ursoc the utopia slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the urclav and ursoc signals). ? 8 6 7 figure 60. utopia slave receive timing ?
sgus050a ? january 2004 ? revised march 2004 127 post office box 1443 ? houston, texas 77251?1443 timer timing timing requirements for timer inputs ? (see figure 61) no. min max unit 1 t w(tinph) pulse duration, tinp high 8p* ns 2 t w(tinpl) pulse duration, tinp low 8p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. switching characteristics over recommended operating conditions for timer outputs ? (see figure 61) no. parameter min max unit 3 t w(touth) pulse duration, tout high 8p ?3* ns 4 t w(toutl) pulse duration, tout low 8p ?3* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. tinpx toutx 4 3 2 1 figure 61. timer timing
sgus050a ? january 2004 ? revised march 2004 128 post office box 1443 ? houston, texas 77251?1443 general-purpose input/output (gpio) port timing timing requirements for gpio inputs ?? (see figure 62) no. min max unit 1 t w(gpih) pulse duration, gpix high 8p* ns 2 t w(gpil) pulse duration, gpix low 8p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. ? the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have the dsp reco gnize the gpix changes through software polling of the gpio register, the gpix duration must be extended to at least 12p to allow the dsp enough time to access the gpio register through the cfgbus. switching characteristics over recommended operating conditions for gpio outputs ? (see figure 62) no. parameter min max unit 3 t w(gpoh) pulse duration, gpox high 32p* ns 4 t w(gpol) pulse duration, gpox low 32p* ns *this parameter is not production tested. ? p = 1/cpu clock frequency in ns. for example, when running parts at 600 mhz, use p = 1.67 ns. gpix gpox 4 3 2 1 figure 62. gpio port timing
sgus050a ? january 2004 ? revised march 2004 129 post office box 1443 ? houston, texas 77251?1443 jtag test-port timing timing requirements for jtag test port (see figure 63) no. min max unit 1 t c(tck) cycle time, tck 35* ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 10* ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 9* ns *this parameter is not production tested. switching characteristics over recommended operating conditions for jtag test port (see figure 63) no. parameter min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid ?3* 18* ns *this parameter is not production tested. tck tdo tdi/tms/trst 1 2 3 4 2 figure 63. jtag test-port timing
sgus050a ? january 2004 ? revised march 2004 130 post office box 1443 ? houston, texas 77251?1443 mechanical data gad (s-cpga-p570) ceramic pin grid array notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. flip chip application only d. this package is hermetically sealed with a metal lid. thermal resistance characteristics (s-cpga package) no c/w 1 r ja junction-to-free air (low k jedec pcb) 20.96 2 r ja junction-to-free air (high k jedec pcb) 16.5 3 r jc junction-to-case (high k jedec pcb with heat sink on lid) 10.9 4 r jc junction-to-case (high k jedec pcb with heat sink on body) 7.69 5 r jb junction-to-board (high k jedec pcb) 9 6 r jb junction-to-board (high k jedec pcb with thermal compound on top of the die) 2.93
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-0324501qxa active fcpga gad 570 1 tbd call ti level-nc-nc-nc sm320c6415dgadw60 active fcpga gad 570 8 tbd call ti level-nc-nc-nc smj320c6415dgadw60 active fcpga gad 570 1 tbd call ti level-nc-nc-nc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 30-mar-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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